?? regkeys
字號:
sprop_294_namePROP_ISimSpecifySearchDirectorysprop_294_val""sprop_295_namePROP_ISimSpecifySearchDirectorysprop_295_val""sprop_296_namePROP_ISimSpecifySearchDirectorysprop_296_val""sprop_297_namePROP_ISimSpecifySearchDirectorysprop_297_val""sprop_298_namePROP_ISimSpecifySearchDirectorysprop_298_val""sprop_299_namePROP_ISimSpecifySearchDirectorysprop_299_val""sprop_29_namePROP_SimModelRetainHierarchysprop_29_val"true"sprop_2_namePROP_Top_Level_Module_Typesprop_2_val"HDL"sprop_300_namePROP_ISimSpecifyDefMacroAndValuesprop_300_val""sprop_301_namePROP_ISimSpecifyDefMacroAndValuesprop_301_val""sprop_302_namePROP_ISimSpecifyDefMacroAndValuesprop_302_val""sprop_303_namePROP_ISimSpecifyDefMacroAndValuesprop_303_val""sprop_304_namePROP_ISimSpecifyDefMacroAndValuesprop_304_val""sprop_305_namePROP_ISimSpecifyDefMacroAndValuesprop_305_val""sprop_306_namePROP_ISimSpecifyDefMacroAndValuesprop_306_val""sprop_307_namePROP_ISimSpecifyDefMacroAndValuesprop_307_val""sprop_308_namePROP_ISimSpecifyDefMacroAndValuesprop_308_val""sprop_309_namePROP_ISimSpecifyDefMacroAndValuesprop_309_val""sprop_30_namePROP_SynthOptsprop_30_val"Speed"sprop_310_namePROP_ISimSpecifyDefMacroAndValuesprop_310_val""sprop_311_namePROP_xstVeriIncludeDirsprop_311_val""sprop_312_namePROP_xstVeriIncludeDirsprop_312_val""sprop_313_namePROP_ISimSpecifySearchDirsprop_313_val""sprop_314_namePROP_ISimSpecifySearchDirsprop_314_val""sprop_315_namePROP_DevFamilysprop_315_val"Spartan3"sprop_316_namePROP_Simulatorsprop_316_val"ISE Simulator (VHDL/Verilog)"sprop_317_namePROP_SmartGuideFileNamesprop_317_val"SR_Latch_top_guide.ncd"sprop_318_namePROP_SimModelRenTopLevInstTosprop_318_val"UUT"sprop_319_namePROP_SynthConstraintsFilesprop_319_val""sprop_31_namePROP_SynthOptEffortsprop_31_val"Normal"sprop_320_namePROP_ISimCustomSimCmdFileName_par_tbsprop_320_val""sprop_321_namePROP_ISimCustomSimCmdFileName_par_tbwsprop_321_val""sprop_322_namePROP_ISimCustomSimCmdFileName_behav_tbsprop_322_val""sprop_323_namePROP_ISimCustomSimCmdFileName_behav_tbwsprop_323_val""sprop_324_namePROP_ISimCustomSimCmdFileName_gen_tbwsprop_324_val""sprop_325_namePROP_ISimSimulationRun_par_tbsprop_325_val"true"sprop_326_namePROP_ISimSimulationRun_par_tbwsprop_326_val"true"sprop_327_namePROP_ISimSimulationRun_behav_tbsprop_327_val"true"sprop_328_namePROP_ISimSimulationRun_behav_tbwsprop_328_val"true"sprop_329_namePROP_ISimStoreAllSignalTransitions_par_tbsprop_329_val"false"sprop_32_namePROP_xstUseSynthConstFilesprop_32_val"true"sprop_330_namePROP_ISimStoreAllSignalTransitions_par_tbwsprop_330_val"false"sprop_331_namePROP_ISimStoreAllSignalTransitions_behav_tbsprop_331_val"false"sprop_332_namePROP_ISimStoreAllSignalTransitions_behav_tbwsprop_332_val"false"sprop_333_namePROP_ISimGenVCDFile_par_tbsprop_333_val"false"sprop_334_namePROP_ISimGenVCDFile_par_tbwsprop_334_val"false"sprop_335_namePROP_ISimCustomCompilationOrderFilesprop_335_val""sprop_336_namePROP_impactPortsprop_336_val"Auto - default"sprop_337_namePROP_XPowerOptAdvancedVerboseRptsprop_337_val"false"sprop_338_namePROP_XPowerOptMaxNumberLinessprop_338_val"1000"sprop_339_namePROP_xstSafeImplementsprop_339_val"No"sprop_33_namePROP_xstLibSearchOrdersprop_33_val""sprop_340_namePROP_FitterOptimization_xpla3sprop_340_val"Density"sprop_341_namePROP_xcpldFitDesPtermLmt_xbrsprop_341_val"28"sprop_342_namePROP_xcpldFitDesInReg_xbrsprop_342_val"true"sprop_343_namePROP_mapTimingModesprop_343_val"Non Timing Driven"sprop_344_namePROP_xilxMapPackfactorsprop_344_val"100"sprop_345_namePROP_xilxPAReffortLevelsprop_345_val"Standard"sprop_346_namePROP_parTimingModesprop_346_val"Performance Evaluation"sprop_347_namePROP_parGenAsyDlyRptsprop_347_val"false"sprop_348_namePROP_parGenClkRegionRptsprop_348_val"false"sprop_349_namePROP_parGenTimingRptsprop_349_val"true"sprop_34_namePROP_xstCasesprop_34_val"Maintain"sprop_350_namePROP_parGenSimModelsprop_350_val"false"sprop_351_namePROP_parPowerReductionsprop_351_val"false"sprop_352_namePROP_parMpprParIterationssprop_352_val"3"sprop_353_namePROP_parMpprResultsToSavesprop_353_val""sprop_354_namePROP_parMpprResultsDirectorysprop_354_val""sprop_355_namePROP_parMpprNodelistFilesprop_355_val""sprop_356_namePROP_xilxBitgCfg_GenOpt_DbgBitStrsprop_356_val"false"sprop_357_namePROP_xilxBitgReadBk_GenBitStrsprop_357_val"false"sprop_358_namePROP_xilxBitgCfg_GenOpt_LogicAllocFilesprop_358_val"false"sprop_359_namePROP_xilxBitgCfg_GenOpt_MaskFilesprop_359_val"false"sprop_35_namePROP_xstWorkDirsprop_35_val"./xst"sprop_360_namePROP_SynthRAMStylesprop_360_val"Auto"sprop_361_namePROP_xstROMStylesprop_361_val"Auto"sprop_362_namePROP_SynthMuxStylesprop_362_val"Auto"sprop_363_namePROP_xstMoveFirstFfStagesprop_363_val"true"sprop_364_namePROP_xstMoveLastFfStagesprop_364_val"true"sprop_365_namePROP_MapPowerReductionsprop_365_val"false"sprop_366_namePROP_MapEffortLevelsprop_366_val"Medium"sprop_367_namePROP_MapPlacerCostTablesprop_367_val"1"sprop_368_namePROP_MapLogicOptimizationsprop_368_val"false"sprop_369_namePROP_MapRegDuplicationsprop_369_val"false"sprop_36_namePROP_xstIniFilesprop_36_val""sprop_370_namePROP_MapSmartGuideFileNamesprop_370_val"SR_Latch_top_guide.ncd"sprop_371_namePROP_ParSmartGuideFileNamesprop_371_val"SR_Latch_top_guide.ncd"sprop_372_namePROP_DevFamilyPMNamesprop_372_val"spartan3"sprop_373_namePROP_DevDevicesprop_373_val"xc3s200"sprop_374_namePROP_CompxlibSimPathsprop_374_val"Search in Path"sprop_375_namePROP_CompxlibLangsprop_375_val"VHDL"sprop_376_namePROP_SimModelGenMultiHierFilesprop_376_val"false"sprop_377_namePROP_ISimSimulationRunTime_par_tbsprop_377_val"1000 ns"sprop_378_namePROP_ISimSimulationRunTime_par_tbwsprop_378_val"1000 ns"sprop_379_namePROP_ISimSimulationRunTime_behav_tbsprop_379_val"1000 ns"sprop_37_namePROP_xstVerilog2001sprop_37_val"true"sprop_380_namePROP_ISimSimulationRunTime_behav_tbwsprop_380_val"1000 ns"sprop_381_namePROP_ISimVCDFileName_par_tbsprop_381_val"xpower.vcd"sprop_382_namePROP_ISimVCDFileName_par_tbwsprop_382_val"xpower.vcd"sprop_383_namePROP_xilxPARextraEffortLevelsprop_383_val"None"sprop_384_namePROP_parPowerActivityFilesprop_384_val""sprop_385_namePROP_MapPowerActivityFilesprop_385_val""sprop_386_namePROP_MapExtraEffortsprop_386_val"None"sprop_387_namePROP_DevPackagesprop_387_val"ft256"sprop_388_namePROP_Synthesis_Toolsprop_388_val"XST (VHDL/Verilog)"sprop_389_namePROP_CompxlibUniSimLibsprop_389_val"true"sprop_38_namePROP_xstVeriIncludeDir_Globalsprop_38_val""sprop_390_namePROP_CompxlibUni9000Libsprop_390_val"true"sprop_391_namePROP_DevSpeedsprop_391_val"-4"sprop_392_namePROP_PreferredLanguagesprop_392_val"Verilog"sprop_393_namePROP_ChangeDevSpeedsprop_393_val"-4"sprop_394_namePROP_SimModelTargetsprop_394_val"Verilog"sprop_395_namePROP_tbwTestbenchTargetLangsprop_395_val"Verilog"sprop_396_namePROP_xilxPreTrceSpeedsprop_396_val"-4"sprop_397_namePROP_xilxPostTrceSpeedsprop_397_val"-4"sprop_398_namePROP_SimModelRenTopLevArchTosprop_398_val"Structure"sprop_399_namePROP_SimModelGenArchOnlysprop_399_val"false"sprop_39_namePROP_xstUserCompileListsprop_39_val""sprop_3_namePROP_SynthTopsprop_3_val"Module|SR_Latch_top"sprop_400_namePROP_SimModelOutputExtIdentsprop_400_val"false"sprop_401_namePROP_SimModelRenTopLevModsprop_401_val""sprop_402_namePROP_SimModelIncUselibDirInVerilogFilesprop_402_val"false"sprop_403_namePROP_SimModelIncSdfAnnInVerilogFilesprop_403_val"true"sprop_404_namePROP_SimModelNoEscapeSignalsprop_404_val"false"sprop_405_namePROP_netgenPostXlateSimModelNamesprop_405_val"SR_Latch_top_translate.v"sprop_406_namePROP_netgenPostMapSimModelNamesprop_406_val"SR_Latch_top_map.v"sprop_407_namePROP_netgenPostParSimModelNamesprop_407_val"SR_Latch_top_timesim.v"sprop_408_namePROP_bencherPostXlateTestbenchNamesprop_408_val"SR_Latch.translate_tfw"sprop_409_namePROP_bencherPostMapTestbenchNamesprop_409_val"SR_Latch.map_tfw"sprop_40_namePROP_xstGenericsParameterssprop_40_val""sprop_410_namePROP_bencherPostParTestbenchNamesprop_410_val"SR_Latch.timesim_tfw"sprop_411_namePROP_SimModelIncSimprimInVerilogFilesprop_411_val"false"sprop_412_namePROP_SimModelIncUnisimInVerilogFilesprop_412_val"false"sprop_413_namePROP_netgenPostSynthesisSimModelNamesprop_413_val"SR_Latch_top_synthesis.v"sprop_414_namePROP_SimModelAutoInsertGlblModuleInNetlistsprop_414_val"true"sprop_415_namePROP_PostXlateSimModelNamesprop_415_val"SR_Latch_top_translate.v"sprop_416_namePROP_PostMapSimModelNamesprop_416_val"SR_Latch_top_map.v"sprop_417_namePROP_PostParSimModelNamesprop_417_val"SR_Latch_top_timesim.v"sprop_418_namePROP_PostParSimModelNamesprop_418_val"SR_Latch_top_timesim.v"sprop_419_namePROP_PostParSimModelNamesprop_419_val"SR_Latch_top_timesim.v"sprop_41_namePROP_xstVerilogMacrossprop_41_val""sprop_420_namePROP_tbwPostXlateTestbenchNamesprop_420_val"SR_Latch.translate_tfw"sprop_421_namePROP_tbwPostMapTestbenchNamesprop_421_val"SR_Latch.map_tfw"sprop_422_namePROP_tbwPostParTestbenchNamesprop_422_val"SR_Latch.timesim_tfw"sprop_423_namePROP_tbwPostParTestbenchNamesprop_423_val"SR_Latch.timesim_tfw"sprop_424_namePROP_PostSynthesisSimModelNamesprop_424_val"SR_Latch_top_synthesis.v"sprop_425_namePROP_SimModelBringOutGtsNetAsAPortsprop_425_val"false"sprop_426_namePROP_SimModelBringOutGsrNetAsAPortsprop_426_val"false"sprop_427_namePROP_netgenRenameTopLevEntTosprop_427_val""sprop_428_namePROP_SimModelPathUsedInSdfAnnsprop_428_val"Default"sprop_42_namePROP_xst_otherCmdLineOptionssprop_42_val""sprop_43_namePROP_xstGenerateRTLNetlistsprop_43_val"Yes"sprop_44_namePROP_xstHierarchySeparatorsprop_44_val"/"sprop_45_namePROP_xstBusDelimitersprop_45_val"<>"sprop_46_namePROP_SynthFsmEncodesprop_46_val"Auto"sprop_47_namePROP_SynthCaseImplStylesprop_47_val"None"sprop_48_namePROP_SynthResSharingsprop_48_val"true"sprop_49_namePROP_SynthExtractMuxsprop_49_val"Yes"sprop_4_namePROP_BehavioralSimTopsprop_4_val"Module|SR_Latch_top"sprop_50_namePROP_xilxSynthAddIObufsprop_50_val"true"sprop_51_namePROP_xstEquivRegRemovalsprop_51_val"true"sprop_52_namePROP_ISimUutInstNamesprop_52_val"UUT"sprop_53_namePROP_ISimUseCustomSimCmdFile_par_tbsprop_53_val"false"sprop_54_namePROP_ISimUseCustomSimCmdFile_par_tbwsprop_54_val"false"sprop_55_namePROP_ISimUseCustomSimCmdFile_behav_tbsprop_55_val"false"sprop_56_namePROP_ISimUseCustomSimCmdFile_behav_tbwsprop_56_val"false"sprop_57_namePROP_ISimUseCustomSimCmdFile_gen_tbwsprop_57_val"false"sprop_58_namePROP_isimIncreCompilationsprop_58_val"true"sprop_59_namePROP_isimCompileForHdlDebugsprop_59_val"true"sprop_5_namePROP_PostXlateSimTopsprop_5_val"Module|SR_Latch"sprop_60_namePROP_ISimSDFTimingToBeReadsprop_60_val"Setup Time"sprop_61_namePROP_isimValueRangeChecksprop_61_val"false"sprop_62_namePROP_isimSpecifySearchDirectorysprop_62_val""sprop_63_namePROP_ISimSpecifySearchDirectoryChkSyntaxsprop_63_val""sprop_64_namePROP_isimSpecifyDefMacroAndValuesprop_64_val""sprop_65_namePROP_ISimSpecifyDefMacroAndValueChkSyntaxsprop_65_val""sprop_66_namePROP_ISimLibSearchOrderFilesprop_66_val""sprop_67_namePROP_ISimUseCustomCompilationOrdersprop_67_val"false"sprop_68_namePROP_ISimOtherCompilerOptions_behavsprop_68_val""sprop_69_namePROP_ISimOtherCompilerOptions_parsprop_69_val""sprop_6_namePROP_PostMapSimTopsprop_6_val"Module|SR_Latch"sprop_70_namePROP_ISimOtherCompilerOptions_fitsprop_70_val""sprop_71_namePROP_ibiswriterShowAllModelssprop_71_val"false"sprop_72_namePROP_ImpactProjectFilesprop_72_val"Default"sprop_73_namePROP_ngdbuild_otherCmdLineOptionssprop_73_val""sprop_74_namePROP_SynthXORCollapsesprop_74_val"true"sprop_75_namePROP_xilxNgdbld_AULsprop_75_val"false"sprop_76_namePROP_xilxNgdbldMacrosprop_76_val""sprop_77_namePROP_xilxSynthKeepHierarchysprop_77_val"No"sprop_78_namePROP_xstNetlistHierarchysprop_78_val"As Optimized"sprop_79_namePROP_XPowerOptVerboseRptsprop_79_val"false"sprop_7_namePROP_PostParSimTopsprop_7_val"Module|SR_Latch"sprop_80_namePROP_XPowerOptLoadXMLFilesprop_80_val"Default"sprop_81_namePROP_XPowerOptOutputFilesprop_81_val"Default"sprop_82_namePROP_XPowerOptLoadVCDFilesprop_82_val"Default"sprop_83_namePROP_XPowerOptLoadPCFFilesprop_83_val"Default"sprop_84_namePROP_XPowerOptInputTclScriptsprop_84_val""sprop_85_namePROP_XPowerOtherXPowerOptssprop_85_val""sprop_86_namePROP_XplorerModesprop_86_val"Off"sprop_87_namePROP_UserEditorPreferencesprop_87_val"ISE Text Editor"sprop_88_namePROP_UserEditorCustomSettingsprop_88_val""sprop_89_namePROP_UserConstraintEditorPreferencesprop_89_val"Constraints Editor"sprop_8_namePROP_PostFitSimTopsprop_8_val""sprop_90_namePROP_FlowDebugLevelsprop_90_val"0"sprop_91_namePROP_FitterReportFormatsprop_91_val"HTML"sprop_92_namePROP_Enable_Message_Capturesprop_92_val"true"sprop_93_namePROP_Enable_Message_Filteringsprop_93_val"false"sprop_94_namePROP_Enable_Incremental_Messagingsprop_94_val"false"sprop_95_namePROP_lockPinsUcfFilesprop_95_val""sprop_96_namePROP_EnableWYSIWYGsprop_96_val"None"sprop_97_namePROP_xcpldUseLocConstsprop_97_val"Always"sprop_98_namePROP_xcpldFitDesInitsprop_98_val"Low"sprop_99_namePROP_xcpldFitDesTimingCstsprop_99_val"true"sprop_9_namePROP_PostSynthSimTopsprop_9_val"Module|SR_Latch"s
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