JDF E
// Created by ISE ver 1.0
PROJECT IrDA
DESIGN irda Normal
DEVKIT XCR3128XL TQ144
DEVFAM xpla3
FLOW XST VHDL
STIMULUS uart_tb.vhd Normal
STIMULUS irda_uart_tb.vhd Normal
MODULE txmit.vhd
MODSTYLE txmit Normal
MODULE sirendec.vhd
MODSTYLE sirendec Normal
MODULE uart.vhd
MODSTYLE uart Normal
MODULE jk_ff.vhd
MODSTYLE jk_ff Normal
MODULE irda_uart.vhd
MODSTYLE irda_uart Normal
MODULE rxcver.vhd
MODSTYLE rxcver Normal
LIBFILE pkg_util.vhd work ***
[STRATEGY-LIST]
Normal=True, 993240160
[Normal]
_VhdlSimCustom_postPar=xstvhd, XPLA3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1016568790, irda_uart_post.do
_VhdlSimDo_postPar=xstvhd, XPLA3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1016566957, False
p_ModelSimSimRunTime=xstvhd, XPLA3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1016556344, 100us
p_VhdlSimDesignUnitName_postPar=xstvhd, XPLA3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1016556344, irda_uart_tb
_VhdlSimCustom_behav=xstvhd, XPLA3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1016570327, irda_uart_func.do
_VhdlSimDo_behav=xstvhd, XPLA3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1016570442, False
p_VhdlSimDesignUnitName_behav=xstvhd, XPLA3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1016568903, irda_uart_tb