-- *******************************************************************
-- 
-- Owner:	Xilinx Inc.
-- File:  	jk_ff.vhd
--
-- Purpose: 	JK flip flop with async. clear  model: 74xx109
--
-- Created:	VHDL code generated by Visual HDL 8-15-01
--  
-- *******************************************************************
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;
 
use work.pkg_util.all;
 
entity jk_ff is
  port (
        clk 	: in STD_LOGIC;
        J 	: in STD_LOGIC;
        K 	: in STD_LOGIC;
        CLR 	: in STD_LOGIC;
        jkout 	: out STD_LOGIC
        );
end jk_ff;
 
 
architecture behavior of jk_ff is
 
-- Created for output, which is read or nets with declaration delay .
signal visual_0_jkout : STD_LOGIC;	

begin
 
  jkout <= visual_0_jkout;
 
  process (clk, CLR)
    variable case_var : STD_LOGIC_VECTOR(1 downto 0);
       -- Generated for case statement
 
  begin
    if not((CLR) = '1' ) then
      visual_0_jkout <= '0';
    elsif (clk'event and clk = '1' ) then
      case_var := STD_LOGIC_VECTOR'((J& K)) ;
      case case_var is
        when "00" =>
          visual_0_jkout <= '0';
        when "01" =>
          visual_0_jkout <= visual_0_jkout;
        when "10" =>
          visual_0_jkout <= not(visual_0_jkout);
        when "11" =>
          visual_0_jkout <= '1';
        when others =>
          null;
      end case  ;
    end if ;
  end process ;
 
 
end ;