-- *******************************************************************-- -- Owner:	Xilinx Inc.-- File:  	irda_uart_tb.vhd---- Purpose: 	Main IrDA and UART test bench. Models inverting-- 		behaviour of incoming IrDA signal.  Tests sending-- 		00 to FF data to the UART and comparing to receive-- 		data being looped.---- Created:	VHDL code generated by Visual HDL 8-15-01--  -- ******************************************************************* library ieee;use ieee.STD_LOGIC_1164.all;use ieee.STD_LOGIC_ARITH.all;use ieee.STD_LOGIC_MISC.all;use ieee.STD_LOGIC_UNSIGNED.all; library work;use work.pkg_util.all; entity irda_uart_tb isend irda_uart_tb; architecture behavior of irda_uart_tb iscomponent irda_uart	port (	      data 		: inout STD_LOGIC_VECTOR (7 downto 0);	      mclkx16 		: in 	STD_LOGIC;	      write 		: in 	STD_LOGIC;	      read 		: in 	STD_LOGIC;	      reset 		: in 	STD_LOGIC;	      parity_error 	: out 	STD_LOGIC;	      framing_error 	: out 	STD_LOGIC;	      overrun 		: out 	STD_LOGIC;	      rxrdy 		: out 	STD_LOGIC;	      txrdy 		: out 	STD_LOGIC;	      irtxd 		: out 	STD_LOGIC;	      irrxd 		: in	 STD_LOGIC 	      );end component;signal mclkx16 	: STD_LOGIC;signal read 	: STD_LOGIC;signal write 	: STD_LOGIC;signal irrxd 	: STD_LOGIC;signal reset 	: STD_LOGIC;signal data 	: STD_LOGIC_VECTOR(7 downto 0 );signal irtxd 	: STD_LOGIC;signal rxrdy 	: STD_LOGIC;signal txrdy 	:  STD_LOGIC;signal parity_error 	: STD_LOGIC;signal framing_error 	: STD_LOGIC;signal overrun 		: STD_LOGIC;constant baudrate 	: INTEGER := 500;constant CLK_BAUD	: TIME := 15625 ps;signal testdata 	: INTEGER := 0;begin          --  Instantiate IrDA/UART top level module        -- irda_uart_test: irda_uart		  UUT: irda_uart        port map (                  data 		=> data,                  mclkx16 	=> mclkx16,                  write 	=> write,                  read 		=> read,                  reset 	=> reset,                  parity_error 	=> parity_error,                  framing_error => framing_error,                  overrun 	=> overrun,                  rxrdy 	=> rxrdy,                  txrdy 	=> txrdy,                  irtxd 	=> irtxd,                  irrxd 	=> irrxd );                                            --  Generate 16 times baudrate clock frequency, i.e. Baudrate = mclkx16/16        process        begin                mclkx16 <= '1';                loop                         --  Divide baudrate periode by 32 to get half mclkx16 period                        wait for CLK_BAUD;                        mclkx16 <= not(mclkx16);                                        end loop ;        wait;        end process ;               --  Reset UART        process        begin                reset <= '1'; 		wait for 2 us;                reset <= '0';       	 	wait;       	 	        end process ;          --  Feeding back transmit output to receive input        process (irtxd)         begin                irrxd <= not(irtxd);        end process ;          --  Main test program        process                variable data_received : STD_LOGIC_VECTOR(7 downto 0);        variable data_written : STD_LOGIC_VECTOR(7 downto 0);                begin                data <= (others => 'Z');                write <= '1'; 	 	--  Deassert write initially                read <= '1';  		--  Deassert read initially 		wait for 3 us; 		                --  Wait for reset to go low                --  Write every possible combinations to the transmitter.                for testdata in 0 to 128 loop                                      		data <= (others => 'Z');                        wait for 50 ns;  			data <= conv_STD_LOGIC_VECTOR(testdata,abs(7-0)+1);                        wait for 20 ns;                                                write <= '0';                        wait for 200 ns;  			write <= '1';                                                --  Latch contents of data bus                        data_written := conv_STD_LOGIC_VECTOR(testdata,abs(7-0)+1);  				wait for 20 ns;                         data <= (others => 'Z');                                                --  Wait for rxrdy/read signal                        if not ((rxrdy) = '1' ) then                                      			wait  until (rxrdy) = '1' ;               		end if;                                      	read <= '0'; 			wait for 25 ns; 			 			--  Latch contents of data bus	                	data_received := data;  	 			wait for 75 ns; 			                	read <= '1';                	                	assert (data_received = data_written)			report "WARNING: received data does not match written data\n"			severity WARNING;                	        	end loop;				wait;		end process ;  end ;