-- *******************************************************************
-- 
-- Owner:	Xilinx Inc.
-- File:  	uart_tb.vhd
--
-- Purpose: 	UART test bench.  Tests sending 00 to FF data
-- 		test cases to transmitter and loops data back
-- 		to receiver and compares incoming data.
--
-- Created:	VHDL code generated by Visual HDL 8-15-01
--  
-- *******************************************************************

 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;

use WORK.pkg_util.all; 
 
entity uart_tb is
end uart_tb;
 
architecture behavior of uart_tb is
 
 
constant BAUDRATE : TIME := 500 nS;
 
component uart
 	port (
            mclkx16 		: in 	STD_LOGIC;
            reset 		: in 	STD_LOGIC;
            read 		: in 	STD_LOGIC;
            write 		: in 	STD_LOGIC;
            data 		: inout STD_LOGIC_VECTOR (7 downto 0);
            sin 		: in 	STD_LOGIC;
            sout 		: out 	STD_LOGIC;
            rxrdy 		: out 	STD_LOGIC;
            txrdy 		: out 	STD_LOGIC;
            parity_error 	: out 	STD_LOGIC;
            framing_error 	: out 	STD_LOGIC;
            overrun 		: out 	STD_LOGIC
            );
            
end component;
  
signal mclkx16 : STD_LOGIC;
signal read : STD_LOGIC;
signal write : STD_LOGIC;
signal rx : STD_LOGIC;
signal reset : STD_LOGIC;
signal data : STD_LOGIC_VECTOR(7 downto 0);
signal tx : STD_LOGIC;
signal rxrdy : STD_LOGIC;
signal txrdy : STD_LOGIC;
signal parityerr : STD_LOGIC;
signal framingerr : STD_LOGIC;
signal overrun : STD_LOGIC;
signal i : INTEGER := 0;


begin
 
 
  --  Instantiate UART top level module
  uart_test: uart
    port map (
              mclkx16 		=> mclkx16,
              reset 		=> reset,
              read 		=> read,
              write 		=> write,
              data 		=> data,
              sin 		=> rx,
              sout 		=> tx,
              rxrdy 		=> rxrdy,
              txrdy 		=> txrdy,
              parity_error 	=> parityerr,
              framing_error 	=> framingerr,
              overrun 		=> overrun);
              
--  Generate 16 times baudrate clock frequency, i.e. Baudrate = mclkx16/16
process
begin
       	mclkx16 <= '1';    
    	loop 
 		wait for (BAUDRATE/32);
      	
      		--  Divide baudrate periode by 32 to get half mclkx16 period
     		mclkx16 <= not(mclkx16);
     	
    	end loop ;
	wait;
	
end process;
  
  
--  Initiate reset
process
begin	
	wait for 500 ns;
  	reset <= '1';
  	wait for 2 us;
  	reset <= '0';
	wait;
	
end process;


--  Feeding back transmit output to receive input
process
begin
	wait for 100 ns;
	rx <= tx;
end process;



--  Main test program
process

variable data_received : STD_LOGIC_VECTOR(7 downto 0 );
variable data_written : STD_LOGIC_VECTOR(7 downto 0 );

begin
 	write <= '1';          --  de-assert write initially
  	read <= '1';           --  de-assert read initially
  	wait for 3 us;
  	
	--  Wait for reset to go low
	--  Write every possible combinations to the transmitter.
	for i in 0 to 127 loop
	
	  	write <= '0';
	  	wait for 100 ns;

	  	data <= conv_STD_LOGIC_VECTOR(i,abs(7-0)+1);
	  	wait for 50 ns;

	  	write <= '1';
	  	data_written := conv_STD_LOGIC_VECTOR(i,abs(7-0)+1);  --  Latch contents of data bus	
		wait for 20 ns;

	  	data <= (others => 'Z');
	  	
	  	if not ((rxrdy) = '1' ) then
	  		wait  until (rxrdy) = '1' ;
		end if;
		
		--  Wait for rxrdy/read signal
		read <= '0';
		wait for 25 ns;

		data_received := data; --  Latch contents of data bus
		wait for 75 ns;

		read <= '1';
		
		assert (data_received = data_written)
		report "WARNING: received data does not match written data\n"
		severity WARNING;
	
	end loop;
	
	wait;
	
end process;
 
 
end;