?? graphics_pipeline.flow.rpt
字號:
Flow report for graphics_pipeline
Tue Dec 09 23:28:58 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+------------------------------------------+
; Flow Status ; Successful - Tue Dec 09 23:28:57 2008 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; graphics_pipeline ;
; Top-level Entity Name ; graphics_pipeline ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 23,654 / 33,216 ( 71 % ) ;
; Total combinational functions ; 23,646 / 33,216 ( 71 % ) ;
; Dedicated logic registers ; 2,200 / 33,216 ( 7 % ) ;
; Total registers ; 2200 ;
; Total pins ; 126 / 475 ( 27 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 391,680 / 483,840 ( 81 % ) ;
; Embedded Multiplier 9-bit elements ; 54 / 70 ( 77 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/09/2008 23:02:09 ;
; Main task ; Compilation ;
; Revision Name ; graphics_pipeline ;
+-------------------+---------------------+
+--------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+-----------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+-----------------------------+---------------+-------------+------------+
; AUTO_RAM_RECOGNITION ; Off ; On ; -- ; -- ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; Auto ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 86474408735.122888172603080 ; -- ; -- ; -- ;
; ENABLE_SIGNALTAP ; Off ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.0 ; -- ; -- ; -- ;
; MISC_FILE ; z_buffer.bsf ; -- ; -- ; -- ;
; MISC_FILE ; z_buffer_inst.v ; -- ; -- ; -- ;
; MISC_FILE ; z_buffer_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; z_buffer.inc ; -- ; -- ; -- ;
; MISC_FILE ; z_buffer.cmp ; -- ; -- ; -- ;
; PARTITION_COLOR ; 14622752 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ;
; USE_SIGNALTAP_FILE ; stp1.stp ; -- ; -- ; -- ;
+-------------------------------------+-----------------------------+---------------+-------------+------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:20:54 ; 1.0 ; 280 MB ; 00:20:51 ;
; Fitter ; 00:05:05 ; 1.0 ; 337 MB ; 00:05:03 ;
; Assembler ; 00:00:09 ; 1.0 ; 244 MB ; 00:00:08 ;
; Classic Timing Analyzer ; 00:00:11 ; 1.0 ; 269 MB ; 00:00:10 ;
; Total ; 00:26:19 ; -- ; -- ; 00:26:12 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off graphics_pipeline -c graphics_pipeline
quartus_fit --read_settings_files=off --write_settings_files=off graphics_pipeline -c graphics_pipeline
quartus_asm --read_settings_files=off --write_settings_files=off graphics_pipeline -c graphics_pipeline
quartus_tan --read_settings_files=off --write_settings_files=off graphics_pipeline -c graphics_pipeline --timing_analysis_only
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