為了滿足現(xiàn)代高速通信中頻率快速轉(zhuǎn)換的需求,基于坐標(biāo)旋轉(zhuǎn)數(shù)字計(jì)算(CORDIC,Coordinate Rotation Digital Computer)算法完成正交直接數(shù)字頻率合成(ODDFS,Orthogonal Direct Digital Frequency Synthesizer)電路設(shè)計(jì)方案。采用MATLAB和Xilinx System Generator開(kāi)發(fā)工具搭建電路的系統(tǒng)模型,通過(guò)現(xiàn)場(chǎng)可編程門(mén)陣列(FPGA,F(xiàn)ield Programmable Gate Array)完成電路的寄存器傳輸級(jí)(RTL,Register Transfer Level)驗(yàn)證,仿真結(jié)果表明電路設(shè)計(jì)具有很高的有效性和可行性。
The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both integer-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthesizer.This application note compares the MAX2870 and ADF4350 registers andloop filter design in detail. Users who already familiar with ADF4350 canuse this application note as a quick design reference.