做DSP最應(yīng)該懂得157個(gè)問題（回答） 四.5V/3.3V如何混接？ TI DSP的發(fā)展同集成電路的發(fā)展一樣，新的DSP都是3.3V的，但目前還有許多外圍電路是5V的，因此在DSP系統(tǒng)中，經(jīng)常有5V和3.3V的DSP混接問題。在這些系統(tǒng)中，應(yīng)注意： 1)DSP輸出給5V的電路（如D/A），無需加任何緩沖電路，可以直接連接。 2)DSP輸入5V的信號（如A/D），由于輸入信號的電壓>4V，超過了DSP的電源電壓，DSP的外部信號沒有保護(hù)電路，需要加緩沖，如74LVC245等，將5V信號變換成3.3V的信號。 3)仿真器的JTAG口的信號也必須為3.3V，否則有可能損壞DSP。 五.為什么要片內(nèi)RAM大的DSP效率高？
上傳時(shí)間： 2016-08-29
上傳用戶：佳期如夢
With the advent of multimedia, digital signal processing (DSP) of sound has emerged from the shadow of bandwidth-limited speech processing. Today, the main appli- cations of audio DSP are high quality audio coding and the digital generation and manipulation of music signals. They share common research topics including percep- tual measurement techniques and analysis/synthesis methods. Smaller but nonetheless very important topics are hearing aids using signal processing technology and hardware architectures for digital signal processing of audio. In all these areas the last decade has seen a significant amount of application oriented research.
標(biāo)簽： multimedia processing the digital
上傳時(shí)間： 2014-01-23
上傳用戶：xwd2010
實(shí)現(xiàn)A/D采樣，用于DSP的基礎(chǔ)編程學(xué)習(xí)，開發(fā)語言是c，用的是ccs2.2的軟件
標(biāo)簽： 采樣
上傳時(shí)間： 2016-11-10
上傳用戶：love_stanford
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs.
標(biāo)簽： TMS 320 fixed-point processor
上傳時(shí)間： 2013-12-27
上傳用戶：宋桃子
北京瑞泰DSP系統(tǒng)的指示燈實(shí)驗(yàn)，了解IECTEK-C6713-A板在CE1空間上的擴(kuò)展，掌握發(fā)光二極管的原理和方法
標(biāo)簽： DSP 指示燈 實(shí)驗(yàn)
上傳時(shí)間： 2014-08-23
上傳用戶：450976175
This file (the project file) contains information at the project level and is used to build a single project or subproject. Other users can share the project (.dsp) file, but they
標(biāo)簽： project file information the
上傳時(shí)間： 2013-12-18
上傳用戶：cainaifa
DSP嵌入式系統(tǒng)開發(fā)典型案例 （1）5-1.asm對應(yīng)第五章語音信號的采集和播放主程序； （2）5-2.asm對應(yīng)第五章語音信號的采集和播放中斷向量程序； （3）5-3.cmd對應(yīng)第五章語音信號的采集和播放配置文件； （4）5-4.asm對應(yīng)第五章語音信號的u/A律壓縮程序； （5）5-5.m對應(yīng)第五章語音去噪的仿真程序； （6）5-6.asm對應(yīng)第五章語音去噪的主程序； （7）5-7.c對應(yīng)第五章CVSD編碼的C語言程序代碼； （8）5-8.asm對應(yīng)第五章CVSD的解碼程序； （9）5-9.asm對應(yīng)第五章CVSD的編碼程序。
上傳時(shí)間： 2017-02-17
上傳用戶：123啊
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
標(biāo)簽： synthesize simulator modelsim verilog
上傳時(shí)間： 2014-06-26
上傳用戶：zhuyibin
作者B.A.Shenoi, John Wiley & Sons 出版社出版，主要講述DSP信號處理、濾波器設(shè)計(jì)，書里包含大量matlab實(shí)例。
標(biāo)簽： Shenoi Wiley John Sons
上傳時(shí)間： 2017-05-20
上傳用戶：13215175592
A programmable digital signal processor (PDSP) is a special-purpose microprocessor with specialized architecture and instruction set for implementing DSP algorithms. Typical architectural features include multiple memory partitions (onchip, off-chip, data memory, program memory, etc.), multiple (generally pipelined) arithmetic and logic units (ALUs), nonuniform register sets, and extensive hardware numeric support [1,2]. Single-chip PDSPs have become increasingly popular for real-time DSP applications [3,4].
標(biāo)簽： special-purpose microprocessor programmable specialized
上傳時(shí)間： 2017-08-13
上傳用戶：腳趾頭
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