This Verilog HDL description implements a UART.
標簽： description implements Verilog This
上傳時間： 2013-12-17
上傳用戶：wff
this a Uart source code using Verilog.
上傳時間： 2016-05-19
上傳用戶：zsjzc
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
標簽： description implements Creation Original
上傳時間： 2016-05-27
上傳用戶：1109003457
This is a uart source written by VHDL .widely used and compatible with Whibone.
標簽： compatible Whibone written source
上傳時間： 2013-12-22
上傳用戶：cxl274287265
intercept tty is using for listening a UART conversation
標簽： conversation intercept listening using
上傳時間： 2017-04-12
上傳用戶：wangdean1101
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽： PicoBlaze Create Master Xilinx
上傳時間： 2013-11-05
上傳用戶：a6697238
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽： PicoBlaze Create Master Xilinx
上傳時間： 2013-11-12
上傳用戶：大三三
SDRAM 參考設計:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
標簽： high-level following reference diagram
上傳時間： 2013-12-15
上傳用戶：Miyuki
B300-B300SP2 功能差異.xlsxM531X DM流程_v2.0.pdfM531X HTTP AT指令手冊v1.4.pdfM531X MQTT 使用指導_v1.3.pdfM531X OneNET 參考手冊_v1.6.pdfM5310 & M5310-A差異文檔.pdfM5310A AT Command B300SP5-MH0S04.pdfM5310-A FOTA 升級手冊_v1.0.pdfM5310-A LWM2M AT指令手冊v1.4.pdfM5310-A MBRH0S04更新日志.pdfM5310-A TCPIP應用指導_v1.2.pdfM5310-A UART低功耗應用指導_v1.0.pdfM5310-A_EVB用戶使用指南V1.0.pdfM5310-A-MBRH0S02更新日志.pdfM5310-A-MBRH0S03更新日志.pdfM5310-A參考設計V1.5.pdfM5310-A硬件設計手冊_V1.7.pdfM5310-封裝.zipOneNET 平臺FOTA 升級(NB-IOT)_v1.0.pdf
上傳時間： 2022-06-24
上傳用戶：
Implementing a Software UART on the TMS320C54x with the McBSP and DMA
標簽： Implementing the Software McBSP
上傳時間： 2014-11-30
上傳用戶：tuilp1a
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