The decoding algorithm used in RBDS.c is based on error trapping. The program emulates the operation of the encoder and decoder of a binary cyclic codes, using bitwise shifts and xor for modulo g(x) operations.
The Viterbi algorithm is the same as the binary case with one main difference: The survivor sequences include the uncoded bits, which are decided at each trellis stage when selecting one of two parallel branches with the largest correlation metric.
Presently, only 8-PSK modulation is considered. Extensions to higher-order modulations can be implemented following a similar procedure.
嵌入式系統(tǒng)開發(fā)
TOPPERS and JSP Kernel Release 1.3
TOPPERS = Toyohashi Open Platform for Embedded Real-Time Systems
JSP = Just Standard Profile Kernel
