Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL mode...
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL mode...
采用 DVB反向鏈路(DVB-RCS)標準中的雙二元Turbo碼matlab仿真程序和仿真結果。支持1/2和1/3碼率。支持MAP,LOG-MAP解碼算法。...
max-log-map,DVB-RCS,Turbo,譯碼,程序...
This paper investigates the design of joint frequency offset and carrier phase estimation of a multi-frequency time division multiple access (MF-TDM...
DVB-T 標準及說明 pdf版...