驅動開發向導 I came Across an article QuickSYS which implements an NT driver framework. That article demonstrates a MFC application that gets a project name as a parameter and creates Visual C++ workspace with NT driver framework. I decided to copy the NT driver framework source and to put it in the Visual Studio project wizard as seen above. This is simpler rather than running an external executable application that generates the code for you.
標簽： article implements framework QuickSYS
上傳時間： 2014-01-07
上傳用戶：2467478207
Seamless handover Across Heterogeneous Networks - An IEEE 802.21 Centric Approach.
標簽： Heterogeneous Seamless Approach Networks
上傳時間： 2015-10-20
上傳用戶：ippler8
Peer-to-Peer (P2P) communication Across middleboxes
標簽： communication Peer-to-Peer middleboxes Across
上傳時間： 2014-11-26
上傳用戶：diets
Eigenface and Fisherface Performance Across Pose
標簽： Performance Fisherface Eigenface Across
上傳時間： 2013-11-27
上傳用戶：anng
Video object matching Across multiple independent views using local descriptors and adaptive learning文章描述了多攝像機系統下的目標檢測與跟蹤，和自學習方法。很有參考價值。
標簽： independent descriptors matching adaptive
上傳時間： 2014-01-18
上傳用戶：chongcongying
Abstract: Quartz crystals are mechanical resonators with piezoelectric properties. The piezoelectricproperties (electric potential Across the crystal is proportional to mechanical deformation) allow their use
標簽： 晶體振蕩器
上傳時間： 2013-10-17
上傳用戶：時代將軍
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end Across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
Multiple-voltage electronics systems often requirecomplex supply voltage tracking or sequencing, whichif not met, can result in system faults or even permanentfailures in the fi eld. The design diffi culties in meetingthese requirements are often compounded in distributedpowerarchitectures where point-of-load (POL) DC/DCconverters or linear regulators are scattered Across PCboard space, sometimes on different board planes. Theproblem is that power supply circuitry is often the lastcircuitry to be designed into the board, and it must beshoehorned into whatever little board real estate is left.Often, a simple, drop-in, fl exible solution is needed tomeet these requirements.
上傳時間： 2013-10-08
上傳用戶：15071087253
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end Across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2014-01-24
上傳用戶：s363994250
Libnet is a cross-platform library aimed at game developers. It has an abstract high level API, which encourages developers to make their games portable Across platforms and network types
標簽： cross-platform developers abstract library
上傳時間： 2015-01-14
上傳用戶：ghostparker
