RapidForm Add-In template for Visual C.NET. Using this template project, a user can create RapidForm template conveniently
標簽： RapidForm template project Add-In
上傳時間： 2013-12-26
上傳用戶：love1314
RapidForm Add-In template for Visual C++. Using this template project, a user can create RapidForm template conveniently
標簽： RapidForm template project Add-In
上傳時間： 2015-05-10
上傳用戶：15071087253
FreeJaPoll is a free software that make possible to add in a simple way a web-survey to your own site. FreeJaPoll is a servlet written in Java programming language the program logo (on the right) shows The Duke (Java mascotte) and a duke-like colored chicken...why? Because the word "Poll" in my native language, Italian, is very similar to the corrispective English word "Chiken" -)
標簽： FreeJaPoll web-survey software possible
上傳時間： 2015-05-16
上傳用戶：無聊來刷下
finacial application using excel Add-In c C
標簽： application finacial Add-In excel
上傳時間： 2015-12-21
上傳用戶：zhangyi99104144
Outlook Inspector Explorer Trap Events COM Add-In
標簽： Inspector Explorer Outlook Events
上傳時間： 2014-11-30
上傳用戶：520
Getting Things Done Outlook Add-In 試用版 可以結(jié)合Outlook試用,提高工作效率 安裝前可以調(diào)整系統(tǒng)時間到將來某一天,即可實現(xiàn)延長試用時間
標簽： Outlook Getting Add-In Things
上傳時間： 2014-01-21
上傳用戶：xieguodong1234
MS Office Delphi sample Add-In README
標簽： Delphi Office sample Add-In
上傳時間： 2017-03-07
上傳用戶：陽光少年2016
ADO.NET in a Nutshell is the most complete and concise source of ADO.NET information available. Besides being a valuable reference, this book covers a variety of issues that programmers face when developing web applications or web services that rely on database access. Most examples use Microsoft s C# language. The book s CD includes an Add-In to integrate the reference with Visual Studio .NET help files.
標簽： information ADO NET available
上傳時間： 2015-01-11
上傳用戶：nanfeicui
PCI ExpressTM Architecture Add-In Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標簽： Architecture ExpressTM PCI
上傳時間： 2013-11-03
上傳用戶：gy592333
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and Add-In card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an Add-In card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as Add-In card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標簽： pci PCB 設(shè)計規(guī)范
上傳時間： 2013-10-15
上傳用戶：busterman
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