-
清單1
LSDAA: ADC R16,R16 ;十進制數(shù)（在R16中）左移調(diào)整子程序
ADDAA: IN R6,SREG ;bcd碼相加調(diào)整子程序，先保存相加后的
LDI R17,$66 ;狀態(tài)the old status
ADD R16,R17 ;再將和預(yù)加立即數(shù)$66
IN R17,SREG ;輸入相加后新狀態(tài)(the new status)
OR R6,R17 ;新舊狀態(tài)相或
SBRS R6,0 ;相或后進位置位則跳行
SUBI R16,$60 ;否則減去$60(十位bcd不滿足調(diào)整條件)
SBRS R6,5 ;半進位置位則跳行
SUBI R16,6 ;否則減去$06(個位bcd不滿足調(diào)整條件)
ROR R6 ;向高位BCD返還進位位!
RET
標(biāo)簽：
AVR
單片機實用
程序設(shè)計
上傳時間：
2013-10-08
上傳用戶：zh_901
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Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽：
Base-Station
Applications
Single-Chip
Transceiver
上傳時間：
2013-11-07
上傳用戶：songrui
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This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
標(biāo)簽：
XAPP
PROM
694
讀取
上傳時間：
2013-11-11
上傳用戶：zhouli
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With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
標(biāo)簽：
NIOSII
用戶
定制
指令
上傳時間：
2013-11-07
上傳用戶：swing
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Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom
instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner
loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor.
The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
標(biāo)簽：
Nios
定制
指令
用戶
上傳時間：
2013-10-12
上傳用戶：kang1923
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Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽：
Base-Station
Applications
Single-Chip
Transceiver
上傳時間：
2013-11-05
上傳用戶：超凡大師
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This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
標(biāo)簽：
XAPP
PROM
694
讀取
上傳時間：
2013-10-09
上傳用戶：guojin_0704
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如果用戶現(xiàn)有的是 Protel99SE 。ProtelDXP，Protel2004 版本： 1 在powerpcb 軟件的中打開 PCB 文件，選擇導(dǎo)出 ASCII 文件（export ascii file） ，ascii file 的版本應(yīng)該選擇 3.5 及以下的版本。 2 a 在 Protel99SE 。ProtelDXP ， 選擇 File->Import->在出現(xiàn)的對話框中,選擇文件類型中的PADS Ascil Files (*.ASC)輸入對應(yīng)文件即可 1.powerpcb-->export ascii file--->import ascii file with protel99 se sp5(u must install padsimportor that is an add-on for 99sesp5 which can downloan from protel company ). 2.powerpcb-->export ascii file-->import ascii file in orcad layout-->import max file(orcad pcb file)with protel 99 or 99se.
標(biāo)簽：
pcb
powerPCB
protel
上傳時間：
2013-10-16
上傳用戶：whymatalab
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本程序集是Allen I. Holub所寫的《Compiler Design in C》一書的附隨軟件，其中有作者自己編寫的詞法分析和語法分析工具LeX，occs和LLama，該軟件包還包括一個顯示C語言分析過程的程序
標(biāo)簽：
I.
Compiler
Design
Allen
上傳時間：
2014-01-08
上傳用戶：siguazgb
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PGP Components使用PGP算法的加密控件。(有源代碼）工作在：D2 D3 D4 D5。作者：Michael in der Wiesche
標(biāo)簽：
Components
PGP
Michael
Wiesche
上傳時間：
2013-12-28
上傳用戶：koulian
