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C++在幾乎所有的計算環境中都非常普及，而且可以用于幾乎所有的應用程序。C++從C中繼承了過程化編程的高效性，并集成了面向對象編程的功能。C++在其標準庫中提供了大量的功能。有許多商業C++庫支持數量眾多的操作系統環境和專業應用程序。但因為它的內容太多了，所以掌握C++并不十分容易。本書詳述了C++語言的各個方面，包括數據類型、程序控制、函數、指針、調試、類、重載、繼承、多態性、模板、異常和輸入輸出等內容。每一章都以前述內容為基礎，每個關鍵點都用具體的示例進行詳細的講解。本書基本不需要讀者具備任何C++知識，書中包含了理解C++的所有必要知識，讀者可以從頭開始編寫自己的C++程序。本書也適合于具備另一種語言編程經驗但希望全面掌握C++語言的讀者。
I created all the files under Microsoft Windows so lines are terminated by CR/LF.
In Addition to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code.
為PDG格式,這有pdg閱讀器下載|pdg文件閱讀器下載
標簽：
源代碼
上傳時間：
2013-11-18
上傳用戶：gaoqinwu
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in Addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽：
UltraScale
Xilinx
架構
上傳時間：
2013-11-21
上傳用戶：wxqman
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This white paper discusses how market trends, the need for increased productivity, and new legislation have
accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is
changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to
market. This allows FPGA users to design their own customized safety controllers and provides a significant
competitive advantage over traditional microcontroller or ASIC-based designs.
Introduction
The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in
cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas
around machines such as fast-moving robots, and distributed control systems in process automation equipment such
as those used in petrochemical plants.
The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of
electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing
safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was
developed in the mid-1980s and has been revised several times to cover the technical advances in various industries.
In Addition, derivative standards have been developed for specific markets and applications that prescribe the
particular requirements on functional safety systems in these industry applications. Example applications include
process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC
62304), automotive (ISO 26262), power generation, distribution, and transportation.
圖Figure 1. Local Safety System
標簽：
FPGA
安全系統
上傳時間：
2013-11-14
上傳用戶：zoudejile
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Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In Addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽：
PicoBlaze
Create
Master
Xilinx
上傳時間：
2013-11-12
上傳用戶：大三三
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解壓密碼：www.elecfans.com 隨著微電子技術的迅速發展以及集成電路規模不斷提高，對電路性能的設計
要求越來越嚴格，這勢必對用于大規模集成電路設計的EDA 工具提出越來越高的
要求。自1972 年美國加利福尼亞大學柏克萊分校電機工程和計算機科學系開發
的用于集成電路性能分析的電路模擬程序SPICE（Simulation Program with IC
Emphasis）誕生以來，為適應現代微電子工業的發展，各種用于集成電路設計的
電路模擬分析工具不斷涌現。HSPICE 是Meta-Software 公司為集成電路設計中
的穩態分析，瞬態分析和頻域分析等電路性能的模擬分析而開發的一個商業化通
用電路模擬程序，它在柏克萊的SPICE（1972 年推出），MicroSim公司的PSPICE
（1984 年推出）以及其它電路分析軟件的基礎上，又加入了一些新的功能，經
過不斷的改進，目前已被許多公司、大學和研究開發機構廣泛應用。HSPICE 可
與許多主要的EDA 設計工具，諸如Candence,Workview 等兼容，能提供許多重要
的針對集成電路性能的電路仿真和設計結果。采用HSPICE 軟件可以在直流到高
于100MHz 的微波頻率范圍內對電路作精確的仿真、分析和優化。在實際應用中，
HSPICE能提供關鍵性的電路模擬和設計方案，并且應用HSPICE進行電路模擬時，
其電路規模僅取決于用戶計算機的實際存儲器容量。
The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In Addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
標簽：
download
hspice
2007
上傳時間：
2013-10-18
上傳用戶：s363994250
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介紹幾種cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In Addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.
標簽：
architecture
introducin
peripheral
improves
上傳時間：
2015-03-15
上傳用戶：ccclll
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VC技術內幕第五版_English.The 6.0 release of Visual C++ shows Microsoft s continued focus on Internet technologies and COM, which are key components of the new Windows Distributed interNet Application Architecture (DNA). In Addition to supporting these platform initiatives, Visual C++ 6.0 also adds an amazing number of productivity-boosting features such as Edit And Continue, IntelliSense, AutoComplete, and code tips. These features take Visual C++ to a new level. We have tried to make sure that this book keeps you up to speed on the latest technologies being introduced into Visual C++.
標簽：
Microsoft
continued
Internet
English
上傳時間：
2013-12-08
上傳用戶：lepoke
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This firmware translates a PS/2 mouse to a USB mouse. The translator
firmware is entirely interrupt driven (with the exception of sending the
data via USB to the host.) An interrupt is generated when the PS/2 start
bit is received, at which time the firmware will begin its receive routine.
In Addition to this interrupt, every 168ms a timer overflow interrupts the
main program and implements one state of the mouse state machine. This
state machine handles sending bytes to and translating bytes received from
the PS/2 mouse automatically. All of this is done in the background while
the main program runs in the foreground. The only operation that the main
program implements is sending mouse data to the PC via USB.
標簽：
firmware
mouse
translates
translator
上傳時間：
2015-04-26
上傳用戶：cuiyashuo
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Frequency Scale Conversion
From f To f Scale
frq2mel mel2frq mel The mel scale is based on the human perception of sinewave pitch.
frq2erb erb2frq erb The erb scale is based on the equivalent rectangular bandwidths of the human ear.
frq2midi midi2frq midi The midi standard specifies a numbering of semitones with middle C being 60. They can use the normal equal tempered scale or else the pythagorean scale of just intonation. They will in Addition output note names in a character format.
標簽：
Scale
Conversion
Frequency
mel
上傳時間：
2015-06-07
上傳用戶：
-
YSS915 (KP2V2) is an LSI for processing Karaoke voice signals.
This LSI has an A/D converter (1 channel) for the microphone echo, and a memory for the microphone echo and
key control. These features allow achieving the functions needed for the Karaoke system by using only one LSI
chip. As for the microphone echoes, many other types of echoes are available in Addition to ordinary ones so that
YSS915 is applicable to various uses.
In Addition to these Karaoke programs, YSS915 is able to provide the Movie & Music programs, with which the
surround effect is applied to the movie and music sources for giving the users more enjoyment.
YSS915 is pin compatible with and register compatible with YSS903 (KP2V).
標簽：
processing
LSI
converter
Karaoke
上傳時間：
2015-06-23
上傳用戶：lijianyu172
