Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally Any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
標簽： Solutions Analog Altera FPGAs
上傳時間： 2013-11-08
上傳用戶：蟲蟲蟲蟲蟲蟲
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in Any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上傳時間： 2013-11-11
上傳用戶：zhouli
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in Any form or by Any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims Any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at Any time. Xilinx assumes no obligation to correct Any errorscontained in the Documentation, or to advise you of Any corrections or updates. Xilinx expressly disclaims Any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上傳時間： 2014-01-13
上傳用戶：竺羽翎2222
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, Any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時間： 2013-12-10
上傳用戶：zgu489
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in Any form or by Any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims Any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at Any time. Xilinx assumes no obligation to correct Any errors contained in the Documentation, or to advise you of Any corrections or updates. Xilinx expressly disclaims Any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標簽： CPLD
上傳時間： 2013-10-22
上傳用戶：李哈哈哈
USB接口控制器參考設計,xilinx提供VHDL代碼 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) Any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT Any WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
上傳時間： 2013-10-12
上傳用戶：windgate
The XPS Ethernetlite peripheral does not provide Any mechanism to access the Ethernet PHYregisters. These registers are used to configure auto negotiation parameters and to obtain PHYstatus. This application note provides reference systems and associated software to accessPHY registers by connecting the serial management bus signals MDC and MDIO to GPIOswhich the software controls directly.
上傳時間： 2013-10-17
上傳用戶：JamesB
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for Any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.
上傳時間： 2013-11-01
上傳用戶：KSLYZ
When I started writing the first edition of RF Power Amplifiers for Wireless Communications,some time back in 1997, it seemed that I was roaming a largely uninhabitedlandscape. For reasons still not clear to me there were few, if Any, otherbooks dedicated to the subject of RF power amplifiers. Right at the same time, however,hundreds of engineers were being assigned projects to design PAs for wirelesscommunications products. It was not, therefore, especially difficult to be successfulwith a book that was fortuitously at the right place and the right time.
標簽： Communications Amplifiers Wireless Edition
上傳時間： 2013-11-12
上傳用戶：YYRR
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. MAny devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually Any application.
上傳時間： 2013-11-15
上傳用戶：努力努力再努力
