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B0

//=== === === === === === === === === === === === === === = //函數說明 //函數名稱：PolyFit //函數功能：最小二乘法曲線擬

//=== === === === === === === === === === === === === === = //函數說明 //函數名稱：PolyFit //函數功能：最小二乘法曲線擬合 //使用方法：double *x ---- 存放n個數據點的X坐標 // double *y ---- 存放n個數據點的Y坐標 // int n -------- 給定數據點個數 // double *a ---- 返回m-1次擬合多項式的m個系數 // int m -------- 擬合多項式的項數，即擬合多項式的最高次為m-1。要求m<=n,且 // m<=20。若m>n或m>20，則本函數自動按m=min{n,20}處理 // double *dt --- dt[0]返回擬合多項式與各數據點誤差的平方和；dt[1]返回擬合多 // 項式與各數據點的誤差絕對值之和；dt[2]返回擬合多項式與各數據 // 點誤差絕對值的最大值 //注意事項：擬合多項式的形式為 y = B0 + b1*(x-Xavr)...

標簽： PolyFit 函數最小二乘法

上傳時間： 2015-07-19

上傳用戶：waizhang
The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero, gen

The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero, generates the flute when the posedge, MD_Counter8One,generates the flute when the negedge.The aim of the module is to generate the mended miller code to be the source of the MillerDecode. 輸入的數據以下降沿采樣，有效輸入范圍為上升沿前一點，輸入數據包括1 B0+有效數據+1 B0 Operating Rule: R_DATAUNCODE must be synchronous with R_ACTIVE

標簽： MD_Counter sub_module 128 generates

上傳時間： 2013-12-30

上傳用戶：Miyuki
FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明使用 FPGA

FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內部的 FIFO 以及程序對該 FIFO 的數據讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數據wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數據wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產生FIFO寫入的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'B0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空，開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'B0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'B0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產生FIFO讀的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'B0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)

標簽： fpga fifo verilog quartus

上傳時間： 2021-12-19

上傳用戶：20125101110