This packet is a IS-95 BASEBAND simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise.
The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
You should run "Simulation.m" function that include all modules.
his packet is a IS-95 BASEBAND simulation for 1 data channel of 9.6 KBps rate.
The simulation is written for static channel and AWGN noise. The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
You should run "Simulation.m" function that include all modules.
This packet is a IS-95 BASEBAND simulation for 1 data channel of 9.6 KBps rate.
The simulation is written for static channel and AWGN noise. The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
This a very simple BASEBAND simulator for SC-FDMA system. This simulator is part of the upcoming book “Single Carrier FDMA: A New Air Interface for Long Term Evolution” (Wiley, Nov. 2008) which I co-authored with professor David J. Goodman at Polytechnic University.
The purpose of this simulator is to give some concrete idea of how SC-FDMA system works. It does lack many realistic and sophisticated features such as channel coding, time-varying fading channel model, soft decision decoding, etc. Regardless, I am hoping that it will help you understand SC-FDMA which is a fairly new development in 3GPP LTE.
In modern design of digital sysytem,FPGAis widely used,particularly in processing BASEBAND and controlling whole system.The core of this system is based on FPGA.
