利用java實現文件的AES加密功能 This Java AES Crypt package contains the Java class es.vocali.util.AESCrypt, which provides file encryption and decryption using aescrypt file format. Requirements The Java AES Crypt package only works in Java 6, but can be easily adapted to Java 5 by replacing the call to NetworkInterface.getHardwareAddress() with something else. In order to use 256 bit AES keys, you must download and install "Java Cryptography Extension (JCE) Unlimited Strength Jurisdiction Policy Files" from http://java.sun.com/javase/downloads/index.jsp
標簽： Java AES AESCrypt contains
上傳時間： 2017-02-11
上傳用戶：kiklkook
Hardware and firmware for a DSP based digital audio MP3 player with USB pen drive funtionality, using a 16-bit fixed point Texas Instruments TMS320 C55x DSP and CompactFlash card. This is an open source and open hardware MP3 player project.
標簽： funtionality Hardware firmware digital
上傳時間： 2017-02-19
上傳用戶：bibirnovis
本文提出了加快發展之路 從理論設計,通過Matlab / Simulink環境 在定點算法對其行為模擬的 在FPGA或定制實現硅片。這個了 實現了netlist移植的Simulink系統 描述成的硬件描述語言[VHDL]。在這個例子中,這個 Simulink-to-VHDL轉換器被設計來使用 代碼來描述結構VHDL系統互連, 允許簡單的行為說明基本模塊。 結果VHDL bit-true交付后代碼 比較定點Simulink仿真模型等效 模擬。
標簽： Simulink netlist Matlab FPGA
上傳時間： 2017-03-09
上傳用戶：duoshen1989
This Telecommunication Standard [TS] describes the detailed mapping from input blocks of 160 speech samples in 13-bit uniform PCM format to encoded blocks of 95, 103, 118, 134, 148, 159, 204, and 244 bits and from encoded blocks of 95, 103, 118, 134, 148, 159, 204, and 244 bits to output blocks of 160 reconstructed speech samples
標簽： Telecommunication describes Standard detailed
上傳時間： 2013-12-12
上傳用戶：cuibaigao
Introduction Matlab is an ideal tool for simulating digital communications systems, thanks to its easy scripting language and excellent data visualization capabilities. One of the most frequent simulation tasks in the field of digital communications is bit-error- rate testing of modems. The bit-error-rate performance of a receiver is a figure of merit that allows different designs to be compared in a fair manner. Performing bit-error-rate testing withMatlab is very simple, but does require some prerequisite knowledge.
標簽： communications Introduction simulating digital
上傳時間： 2017-03-20
上傳用戶：as275944189
This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
標簽： applications development hardware paper
上傳時間： 2013-12-21
上傳用戶：jichenxi0730
forming of a signal, GLONASS system, coherent reception, graph autocorrelation, crosscorrelation function, bit-error probability[SNR]
標簽： crosscorrelation autocorrelation reception coherent
上傳時間： 2013-12-27
上傳用戶：小鵬
Embedded System Design using 8031 microcontroller defines many steps in development of embedded systems using the most popular 8-bit microcontroller using various examples. I hope this would be useful to everyone.
標簽： microcontroller development Embedded embedded
上傳時間： 2017-04-02
上傳用戶：lnnn30
200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache • Linux® , Microsoft® Windows® CE-enabled MMU • 100-MHz System Bus • MaverickCrunch™ Math Engine • Floating Point, Integer, and Signal Processing Instructions • Optimized for digital music compression and decompression algorithms. • Hardware interlocks allow in-line coding. • MaverickKey™ IDs • 32-bit Unique ID can be used for DRM-compliant 128-bit random ID. • Integrated Peripheral Interfaces • 32-bit SDRAM Interface
標簽： 8226 Cache kbyte Instruction
上傳時間： 2017-04-08
上傳用戶：comua
使用FPGA/CPLD設置語音AD、DA轉換芯片AIC23，FPGA/CPLD系統時鐘為24.576MHz 1、AIC系統時鐘為12.288MHz，SPI時鐘為6.144MHz 2、AIC處于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、幀同步在96KHz
上傳時間： 2013-12-20
上傳用戶：二驅蚊器
