概要2 個(gè)對(duì)稱的600MHz 高性能Blackfin 內(nèi)核328K Bytes 片內(nèi)存儲(chǔ)器每個(gè) Blackfin 內(nèi)核包括:2 個(gè)16 位MAC，2 個(gè)40 位ALU，4 個(gè)8 位視頻ALU，以及1 個(gè)40 位移位器RISC 式寄存器和指令模型，編程簡(jiǎn)單，編譯環(huán)境友好先進(jìn)的調(diào)試、跟蹤和性能監(jiān)視內(nèi)核電壓 0.8V-1.2V，片內(nèi)調(diào)壓器可調(diào)兼容 3.3V 及2.5V I/O256 引腳Mini-BGA 和297 引腳PBGA 兩種封裝外設(shè)兩個(gè)并行輸入/輸出外圍接口單元，支持ITU-R 656 視頻數(shù)據(jù)格式，可與ADI 的模擬前端ADC 無縫連接2 個(gè)雙通道全雙工同步串行接口，支持8 個(gè)立體聲I2S 通道2 個(gè)16 通道DMA 控制器和1 個(gè)內(nèi)部存儲(chǔ)器DMA 控制器SPI 兼容端口12 個(gè)通用32-BIt 定時(shí)/計(jì)數(shù)器，支持PWMSPI 兼容端口支持 IrDA 的UART2 個(gè)“看門狗”定時(shí)器48 個(gè)可編程標(biāo)志引腳1x-63x 倍頻的片內(nèi)PLL
標(biāo)簽： Blackfin 嵌入式 對(duì)稱性 多處理器
上傳時(shí)間： 2013-11-06
上傳用戶：YUANQINHUI
The LPC2292/2294 microcontrollers are based on a 16/32-BIt ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-BIt wide memory interface and a unique accelerator architecture enable 32-BIt code execution at the maximum clock rate. For critical code size applications, the alternative 16-BIt Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-BIt timers, 8-channel 10-BIt ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標(biāo)簽： lpc datasheet 2292 2294
上傳時(shí)間： 2014-12-30
上傳用戶：aysyzxzm
Abstract: When people want portable music, they usually rely on battery-powered audio devices. With a BIt of engineeringblood (or curiosity) running in your veins, it is not difficult to build a wireless Bluetooth® stereo audio system that can becontrolled with any device that has a Bluetooth connection and a music player
標(biāo)簽： 無線藍(lán)牙 立體聲 音頻系統(tǒng)
上傳時(shí)間： 2013-10-09
上傳用戶：天空說我在
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-BIt A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時(shí)間： 2013-10-11
上傳用戶：yuchunhai1990
本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè)：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-BIt binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-BIt binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時(shí)間： 2013-11-12
上傳用戶：18711024007
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 BIts - One Stop BIt - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBIt: The clock pulse of the last data BIt is not output to the SCLK pin
上傳時(shí)間： 2013-10-31
上傳用戶：yy_cn
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending BIt is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時(shí)間： 2013-11-11
上傳用戶：gundamwzc
CH451 使用一個(gè)系統(tǒng)時(shí)鐘信號(hào)來同步芯片內(nèi)部的各個(gè)功能部件，例如，當(dāng)系統(tǒng)時(shí)鐘信號(hào)的頻率變高時(shí)，顯示驅(qū)動(dòng)刷新將變快、按鍵響應(yīng)時(shí)間將變短、上電復(fù)位信號(hào)的寬度將變窄、看門狗周期也將變短。一般情況下，CH451 的系統(tǒng)時(shí)鐘信號(hào)是由內(nèi)置的阻容振蕩提供的，這樣就不再需要任何外圍電路，但內(nèi)置RC 振蕩的頻率受電源電壓的影響較大，當(dāng)電源電壓降低時(shí)，系統(tǒng)時(shí)鐘信號(hào)的頻率也隨之降低。在某些實(shí)際應(yīng)用中，可能希望CH451 提供更長(zhǎng)或者更短的顯示刷新周期、按鍵響應(yīng)時(shí)間等，這時(shí)就需要調(diào)節(jié)系統(tǒng)時(shí)鐘信號(hào)的頻率。CH451 提供了CLK 引腳，用于外接阻容振蕩。當(dāng)在CLK 引腳與地GND 之間跨接電容后，系統(tǒng)時(shí)鐘信號(hào)的頻率將變低；當(dāng)在CLK 引腳與正電源VCC 之間跨接電阻后，系統(tǒng)時(shí)鐘信號(hào)的頻率將變高。因?yàn)镃H451 的系統(tǒng)時(shí)鐘信號(hào)被用于芯片內(nèi)部的所有功能部件，所以其頻率不宜進(jìn)行大幅度的調(diào)節(jié)，一般情況下，跨接電容的容量在5pF 至100pF 之間，跨接電阻的阻值在20KΩ至500KΩ之間。跨接一個(gè)47pF 的電容則頻率降低為一半，跨接一個(gè)47KΩ的電阻則頻率升高為兩倍。另外，CH451 的CLK 引腳可以直接輸入外部的系統(tǒng)時(shí)鐘信號(hào)，但外部電路的驅(qū)動(dòng)能力不能小于±2mA。CH451 在CLKO 引腳提供了系統(tǒng)時(shí)鐘信號(hào)的二分頻輸出，對(duì)于一些不要求精確定時(shí)的實(shí)際應(yīng)用，可以由CLKO 引腳向單片機(jī)提供時(shí)鐘信號(hào)，簡(jiǎn)化外圍電路。 單片機(jī)接口程序下面提供了U1（MCS-51 單片機(jī)）與U2（CH451）的接口程序，供參考。;**********************;需要主程序定義的參數(shù)CH451_DCLK BIt P1.7 ;串行數(shù)據(jù)時(shí)鐘,上升沿激活CH451_DIN BIt P1.6 ;串行數(shù)據(jù)輸出,接CH451 的數(shù)據(jù)輸入CH451_LOAD BIt P1.5 ;串行命令加載,上升沿激活CH451_DOUT BIt P3.2 ;INT0,鍵盤中斷和鍵值數(shù)據(jù)輸入,接CH451 的數(shù)據(jù)輸出CH451_KEY DATA 7FH ;存放鍵盤中斷中讀取的鍵值
標(biāo)簽： 451 ch 數(shù)碼管 實(shí)例程序
上傳時(shí)間： 2013-11-22
上傳用戶：671145514
#include <reg51.h>#include <main.h>#include <interrupt.h> cs5460a應(yīng)用電路(含源程序)BIt code table_odd_even_BIt[16]={0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0}; extern uchar rs485_timeout,pointer_buf485;extern uchar rs485_buf[MAX_485_LEN];extern uchar idata spi_buf[MAX_SPI_LEN];extern uchar pointer_send,send_len; extern uchar count_1s;//extern uint count_2min;extern uint count_10s;extern uchar oper_len,send_offset,chk_sum,send_i;extern BIt flag_send_data,flag_level,flag_drdy,flag_data_ok;
上傳時(shí)間： 2014-01-24
上傳用戶：heart_2007
12864液晶時(shí)鐘顯示程序 LCD 地址變量 ;**************變量的定義***************** RS BIt P2.0 ;LCD數(shù)據(jù)/命令選擇端(H/L) RW BIt P2.1 ;LCD讀/寫選擇端(H/L) EP BIt P2.2 ;LCD使能控制 PSB EQU P2.3 RST EQU P2.5 PRE BIt P1.4 ;調(diào)整鍵(K1) ADJ BIt P1.5 ;調(diào)整鍵(K2) COMDAT EQU P0 LED EQU P0.3 YEAR DATA 18H ;年,月,日變量 MONTH DATA 19H DATE DATA 1AH WEEK DATA 1BH HOUR DATA 1CH ;時(shí),分,秒,百分之一秒變量 MIN DATA 1DH SEC DATA 1EH SEC100 DATA 1FH STATE DATA 23H LEAP BIt STATE.1 ;是否閏年標(biāo)志1--閏年，0--平年 KEY_S DATA 24H ;當(dāng)前掃描鍵值 KEY_V DATA 25H ;上次掃描鍵值 DIS_BUF_U0 DATA 26H ;LCD第一排顯示緩沖區(qū) DIS_BUF_U1 DATA 27H DIS_BUF_U2 DATA 28H DIS_BUF_U3 DATA 29H DIS_BUF_U4 DATA 2AH DIS_BUF_U5 DATA 2BH DIS_BUF_U6 DATA 2CH DIS_BUF_U7 DATA 2DH DIS_BUF_U8 DATA 2EH DIS_BUF_U9 DATA 2FH DIS_BUF_U10 DATA 30H DIS_BUF_U11 DATA 31H DIS_BUF_U12 DATA 32H DIS_BUF_U13 DATA 33H DIS_BUF_U14 DATA 34H DIS_BUF_U15 DATA 35H DIS_BUF_L0 DATA 36H ;LCD第三排顯示緩沖區(qū) DIS_BUF_L1 DATA 37H DIS_BUF_L2 DATA 38H DIS_BUF_L3 DATA 39H DIS_BUF_L4 DATA 3AH DIS_BUF_L5 DATA 3BH DIS_BUF_L6 DATA 3CH DIS_BUF_L7 DATA 3DH DIS_BUF_L8 DATA 3EH DIS_BUF_L9 DATA 3FH DIS_BUF_L10 DATA 40H DIS_BUF_L11 DATA 41H DIS_BUF_L12 DATA 42H DIS_BUF_L13 DATA 43H DIS_BUF_L14 DATA 44H DIS_BUF_L15 DATA 45H FLAG DATA 46H ;1-年，2-月，3-日，4-時(shí)，5-分，6-秒，7-退出調(diào)整。 DIS_H DATA 47H DIS_M DATA 48H DIS_S DATA 49H
標(biāo)簽： 12864 單片機(jī) 液晶時(shí)鐘 顯示程序
上傳時(shí)間： 2013-11-09
上傳用戶：xingisme
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