The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to implement the digital DC/DC Converters have been researched. The function module, state machine of digital DC/DC controller and high resolution DPWM with Sigma- Delta dither has been introduced. They are verified by experiments on a 20 W, 300 KHz non-isolated synchronous buck converters.
標簽： Converters controller optimized Digital
上傳時間： 2013-12-31
上傳用戶：tzl1975
these notes give an overview of beyond C to java and a good idea on how to develop applications in java
標簽： applications overview develop beyond
上傳時間： 2013-12-24
上傳用戶：秦莞爾w
UCSC Kestrel and Beyond寫的一篇關于SIMD的講義,很好,很使用,也可以作為一個PPT模板使用的經典例子哦
上傳時間： 2017-08-04
上傳用戶：zhouchang199
compuete the fast fourier transformation of the image. it is very fast compare than fourier transformation.
標簽： fourier fast transformation the
上傳時間： 2017-08-08
上傳用戶：zhaoq123
9、優先級隊列 QueueNode.h Compare.h PriorityQueue.h Test.cpp 10、串 88 MyString.h MyString.cpp test.cpp 11、二叉樹 BinTreeNode.h BinaryTree.h Test.cpp 12、線索二叉樹 ThreadNode.h ThreadTree.h ThreadInorderIterator.h test.cpp
標簽： MyString PriorityQueue QueueNode cpp
上傳時間： 2014-08-05
上傳用戶：zhangyi99104144
beyond conpare 綠色版，代碼對比工具
上傳時間： 2020-02-21
上傳用戶：young_yzq
隨著第三代移動通信系統(3G)向商業化的邁進，以及超三代(Beyond 3G) 或被稱之為第四代(4G)移動通信系統的發展，對更高速率、更大容量和更好服務質量的通信系統的需求正在不斷增長。另一方面，可利用的無線頻譜資源是有限...
上傳時間： 2013-04-24
上傳用戶：mslj2008
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上傳時間： 2013-10-25
上傳用戶：banyou
Many 8-bit and 16-bit microcontrollers feature 10-bitinternal ADCs. A few include 12-bit ADCs, but these oftenhave poor or nonexistent AC specifi cations, and certainlylack the performance to meet the needs of an increasingnumber of applications. The LTC®2366 and its slowerspeed versions offer a high performance alternative, asshown in the AC specifi cations in Table 1. Compare theseguaranteed specifi cations with the ADC built into yourcurrent microcontroller.
上傳時間： 2013-10-26
上傳用戶：jackandlee
