This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate.
The simulation is written for static channel and AWGN noise. The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
In this letter, the error performance of an ultra-wideband (UWB) system with a hybrid pulse amplitude and position modulation (PAPM) scheme over indoor lognormal fading channels is analyzed. In the PAPM UWB system, input data is modulated onto both the pulse amplitudes and pulse positions.
The SST89E516RDx and SST89V516RDx are members
of the FlashFlex51 family of 8-bit microcontroller products
designed and manufactured with SST’s patented and proprietary
SuperFlash CMOS semiconductor process technology.
The split-gate cell design and thick-oxide tunneling
injector offer significant cost and reliability benefits for SST’s
customers. The devices use the 8051 instruction set and
are pin-for-pin compatible with standard 8051 microcontroller
devices.
