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Bit-Plane-Decomposition

  • at89c52 pdf

    The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.

    標簽: 89c c52 at

    上傳時間: 2013-11-10

    上傳用戶:1427796291

  • 自動檢測單片機80C51串行通訊時的波特率

    自動檢測80C51 串行通訊中的波特率本文介紹一種在80C51 串行通訊應用中自動檢測波特率的方法。按照經驗,程序起動后所接收到的第1 個字符用于測量波特率。這種方法可以不用設定難于記憶的開關,還可以免去在有關應用中使用多種不同波特率的煩惱。人們可以設想:一種可靠地實現自動波特檢測的方法是可能的,它無須嚴格限制可被確認的字符。問題是:在各種的條件下,如何可以在大量允許出現的字符中找出波特率的定時間隔。顯然,最快捷的方法是檢測一個單獨位時間(single bit time),以確定接收波特率應該是多少。可是,在RS-232 模式下,許多ASCII 字符并不能測量出一個單獨位時間。對于大多數字符來說,只要波特率存在合理波動(這里的波特率是指標準波特率),從起始位到最后一位“可見”位的數據傳輸周期就會在一定范圍內發生變化。此外,許多系統采用8 位數據、無奇偶校驗的格式傳輸ASCII 字符。在這種格式里,普通ASCII 字節不會有MSB 設定

    標簽: 80C51 自動檢測 單片機 串行通訊

    上傳時間: 2013-10-15

    上傳用戶:shirleyYim

  • ISE13.1下載配置過程

    介紹ISE13.1 iMPACT 下載bit文件 和mcs文件的詳細步驟

    標簽: 13.1 ISE 配置過程

    上傳時間: 2013-10-22

    上傳用戶:88mao

  • XAPP122 - Spartan-XL FPGA的Express配置

    Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui

    標簽: Spartan-XL Express XAPP FPGA

    上傳時間: 2014-12-28

    上傳用戶:hewenzhi

  • WP200-將Spartan-3 FPGA用作遠程數碼相機的低成本控制器

      The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.

    標簽: Spartan FPGA 200 WP

    上傳時間: 2013-12-10

    上傳用戶:zgu489

  • XAPP719 -利用USR_ACCESS寄存器實現PowerPC高速緩存配置

    The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.

    標簽: USR_ACCESS PowerPC XAPP 719

    上傳時間: 2013-11-13

    上傳用戶:我累個乖乖

  • WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案

    WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs

    標簽: Xilinx FPGA 409 DSP

    上傳時間: 2013-11-07

    上傳用戶:defghi010

  • PLD對FPGA數據加密

    SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?

    標簽: FPGA PLD 數據加密

    上傳時間: 2013-11-06

    上傳用戶:wl9454

  • 各種功能的計數器實例(VHDL源代碼)

    各種功能的計數器實例(VHDL源代碼):ENTITY counters IS  PORT  (   d  : IN  INTEGER RANGE 0 TO 255;   clk  : IN BIT;   clear : IN BIT;   ld  : IN BIT;   enable : IN BIT;   up_down : IN BIT;   qa  : OUT  INTEGER RANGE 0 TO 255;   qb  : OUT  INTEGER RANGE 0 TO 255;   qc  : OUT  INTEGER RANGE 0 TO 255;   qd  : OUT  INTEGER RANGE 0 TO 255;   qe  : OUT  INTEGER RANGE 0 TO 255;   qf  : OUT  INTEGER RANGE 0 TO 255;   qg  : OUT  INTEGER RANGE 0 TO 255;   qh  : OUT  INTEGER RANGE 0 TO 255;   qi  : OUT  INTEGER RANGE 0 TO 255;

    標簽: VHDL 計數器 源代碼

    上傳時間: 2014-11-30

    上傳用戶:半熟1994

  • 6位數微電腦型計數器(48*96mm)

    特點 最高輸入頻率 10KHz 計數速度 50/10000脈波/秒可選擇 四種輸入模式可選擇(加算,減算,加減算,90度相位差加減算) 90度相位差加減算具有提高解析度4倍功能 輸入脈波具有預設刻度功能 計數暫時停止功能 3組報警功能 15BIT類比輸出功能 數位RS-485界面 2:主要規格 脈波輸入型式: Jump-pin selectable current sourcing(NPN) or current sinking (PNP) 脈波觸發電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <10KHz (up,down,up/down mode) <3KHz (quadrature mode) 輸出動作時間 : 0.1 to 99.9 second adjustable 輸出復歸方式: Manual(N) or automatic (R or C) can be modif 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: -199999 to 999999 類比輸出解析度: 15 bit DAC 輸出反應速度: < 1/f+10ms(0-90%) 輸出負載能力: < 10mA for voltage mode < 10V for current mode <[(V+)-7.5V]/20mA for two-wire mode 輸出之漣波: < 0.1% F.S. 通訊位址: "01"-"FF" 傳輸速度: 19200/9600/4800/2400 selective 通信協議: Modbus RTU mode 顯示幕: Red high efficiency LEDs high 14.22mm (.56") 參數設定方式: Touch switches 感應器電源: 12VDC +/-3%(<60mA) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001

    標簽: 48 96 mm 微電腦

    上傳時間: 2013-11-23

    上傳用戶:redmoons

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