8051 Serial I/O Routines Ring Buffered, interrupt-driven UART driver, written in Keil C .
標簽： interrupt-driven Routines Buffered written
上傳時間： 2013-11-27
上傳用戶：330402686
MSP-FET430P140 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK
標簽： Buffered MSP-FET Output Basic
上傳時間： 2015-10-10
上傳用戶：wuyuying
MSP-FET430P120 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10
標簽： Buffered MSP-FET Output Basic
上傳時間： 2013-12-15
上傳用戶：ghostparker
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are Buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are Buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x Buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x Buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready for data operations
標簽： appropriately The endpoints following
上傳時間： 2013-12-02
上傳用戶：dianxin61
RS232.C was written to provide all of the basic functionality needed to employ serial I/O in any application written with Borland C language compilers. Some features are: 1. Ease of use. No assembly language or library files are used and a simple "#include" statement is all that is required to access all of the functions provided. 2. Both input and output are Buffered and interrupt driven for efficiency. 3. Serial ports 1 - 4 are supported on PC, AT and PS/2 compatibles.Chained interrupts used on port 3 and 4 are allowed for so as not to interfere with devices such as a mouse or printer. Transmission speeds of 110 to 115200 baud are available. 4. Detection and utilization of hardware Buffered UARTs (NS16550AF etc.) found in some machines is automatic. 5. Interrupt driven hardware and XON/XOFF flow control is provided for. 6. All source code is included. RS232.C can be used with all memory models.
標簽： functionality provide written employ
上傳時間： 2016-08-24
上傳用戶：小眼睛LSL
All of Java s Input/Output (I/O) facilities are based on streams, which provide simple ways to read and write data of different types. Java provides many different kinds of streams, each with its own application. The universe of streams is divided into four large categories: input streams and output streams, for reading and writing binary data and readers and writers, for reading and writing textual (character) data. You re almost certainly familiar with the basic kinds of streams--but did you know that there s a CipherInputStream for reading encrypted data? And a ZipOutputStream for automatically compressing data? Do you know how to use Buffered streams effectively to make your I/O operations more efficient? Java I/O, 2nd Edition has been updated for Java 5.0 APIs and tells you all you ever need to know about streams--and probably more.
標簽： facilities streams provide Output
上傳時間： 2013-12-17
上傳用戶：6546544
