pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
標簽： outstanding S3C2440A features pccard
上傳時間： 2013-12-24
上傳用戶：lizhen9880
this is a stepper motor controller with specifications pins: for RS-232 interfacing stepper motor: 47-50 bus PUSH button: 9-15 POTEN:9-15
標簽： stepper motor specifications interfacing
上傳時間： 2013-12-22
上傳用戶：lnnn30
observable distribution grid are investigated. A distribution grid is observable if the state of the grid can be fully determined. For the simulations, the modified 34-bus IEEE test feeder is used. The measurements needed for the state estimation are generated by the ladder iterative technique. Two methods for the state estimation are analyzed: Weighted Least Squares and Extended Kalman Filter. Both estimators try to find the most probable state based on the available measurements. The result is that the Kalman filter mostly needs less iterations and calculation time. The disadvantage of the Kalman filter is that it needs some foreknowlegde about the state.
標簽： distribution observable grid investigated
上傳時間： 2014-12-08
上傳用戶：ls530720646
200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache • Linux® , Microsoft® Windows® CE-enabled MMU • 100-MHz System Bus • MaverickCrunch™ Math Engine • Floating Point, Integer, and Signal Processing Instructions • Optimized for digital music compression and decompression algorithms. • Hardware interlocks allow in-line coding. • MaverickKey™ IDs • 32-bit Unique ID can be used for DRM-compliant 128-bit random ID. • Integrated Peripheral Interfaces • 32-bit SDRAM Interface
標簽： 8226 Cache kbyte Instruction
上傳時間： 2017-04-08
上傳用戶：comua
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device鈥檚 cascadable feature allows up to four devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The devices are available in spacesaving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
標簽： electrically programmable provides erasable
上傳時間： 2017-04-09
上傳用戶：cc1015285075
The main MIPS processor of SMP8630 comes with a JTAG interface, allowing: access to caches and data bus (DRAM) with a bandwidth of about 200kbit/s examining the processor state whatever the execution mode (monice) connecting to monice using mdi-server and using a gdb client on the processor to step and break accurately whatever the execution mode running semi-hosted applications fl ash write tool memory testing (MT command) real-time traces: has not been built in CPU (Config3_TL=0) and only supported by MajicPLUS probes (maybe built into emulator?)
標簽： interface processor allowing access
上傳時間： 2013-12-19
上傳用戶：youke111
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
標簽： speed USBHostSlave and Supports
上傳時間： 2014-01-17
上傳用戶：sxdtlqqjl
This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
標簽： This microprocessor describes S3C2410A
上傳時間： 2013-11-30
上傳用戶：GavinNeko
This program requires the DSP2833x header files. // // This program requires an external I2C RTC connected to // the I2C bus at address 0x6f. // // As supplied, this project is configured for "boot to SARAM" // operation. The 2833x Boot Mode table is shown below. // For information on configuring the boot mode of an eZdsp, // please refer to the documentation included with the eZdsp,
標簽： requires program This external
上傳時間： 2017-07-12
上傳用戶：dianxin61
Code Warrior 4.7 Target : MC9S12XS128 Crystal: 16.000Mhz ============================================ 本程序主要包括以下功能： 1.設定系統工作在xxMHZ bus clock時鐘下 2.測試FREESCALEMC9SXS128開發板超頻性能: 如果LED閃爍，說明芯片正常工作 否則，說明芯片沒有正常工作，請檢查系統設計
標簽： Warrior Crystal 16.000 Target
上傳時間： 2013-12-13
上傳用戶：lizhizheng88
