The CC1000 RF transceiver is very easy
to interface with a microcontroller.
The CHIP is configured using a three-wire
bus, comprising of PCLK, PDATA and
PALE signals.
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-CHIP (SOC) development. The IP cores are centered around the common on-CHIP bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
