VHDL implementation of the twofish CIPHER for 128,192 and 256 bit keys.
The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 bit key sizes, along with their respective vector files.
標簽：
implementation
twofish
CIPHER
VHDL
上傳時間：
2017-06-25
上傳用戶：王小奇
