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CLock-based

There are many different (and often confusing) terms associated with CLock-based devices. This appl

There are many different (and often confusing) terms associated with CLock-based devices. This application note attempts to clarify these terms, and hence serves as a comprehensive reference on clock terminology. This application note can be divided into two sections. The first section describes and distinguishes between various clock sources available today. The second section defines and distinguishes between various parameters used to describe clocks. This section also provides methods of measuring some of these parameters.

標(biāo)簽： CLock-based associated different confusing

上傳時(shí)間： 2015-12-02

上傳用戶：sssl
Clock based on the VHDL design language, the revised time alarm can be set up

Clock based on the VHDL design language, the revised time alarm can be set up

標(biāo)簽： the language revised design

上傳時(shí)間： 2013-12-09

上傳用戶：haoxiyizhong
基于AVR單片機(jī)Mega16的電子時(shí)鐘設(shè)計(jì)

Mega16是一款采用先進(jìn)RISC精簡(jiǎn)指令，內(nèi)置A/D的8位單片機(jī)，可支持低電壓聯(lián)機(jī) Flash和EEPROM 寫入功能；同時(shí)還支持 Basic和C 等高級(jí)語(yǔ)言編程。用它設(shè)計(jì)電子時(shí)鐘不僅成本低，硬件簡(jiǎn)單，而且很容易實(shí)現(xiàn)系統(tǒng)移植。介紹了如何利用AVR系列單片機(jī)Mega16及1602字符液晶來(lái)設(shè)計(jì)電子時(shí)鐘的方法，同時(shí)給出了相應(yīng)的電路原理及部分語(yǔ)言程序。 Abstract: ?Mega16 is a high-performance, low power consumption, the use of advanced RISC concise instructions, built-in A/D 8-bit microcontrollers, the on-line support for low-voltage Flash, EEPROM write function. Except Mega16 also support the Basic, C, and other high-level language programming.The electronic clock which is deisgned by Mega16 is not only low-cost, simple hardware, but easy to achieve system migration.The design method of electrioic clock based on the AVR Mega16 and character LCD1602 is introduced in this paper,and the corresponding circuit electrionic and some language program are given.

標(biāo)簽： Mega AVR 16 單片機(jī)

上傳時(shí)間： 2014-12-27

上傳用戶：zl5712176
pic16f8 based clock, it display the time on the TV display. This include source code and sch

pic16f8 based clock, it display the time on the TV display. This include source code and sch

標(biāo)簽： display the include source

上傳時(shí)間： 2015-11-30

上傳用戶：nanfeicui
Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range

Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range from not having any effect on system operation to rendering the system completely non-functional. This application note provides the reader with a clear understanding of jitter in high-speed systems. It introduces the reader to various kinds of jitter in high-speed systems, their causes and their effects, and methods of reducing jitter. This application note will concentrate on jitter in PLL-based frequency synthesizers.

標(biāo)簽： extremely PLL-based important drivers

上傳時(shí)間： 2014-11-25

上傳用戶：asddsd
Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides

Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides a set of recommendations to optimize usage of Cypress clock devices in a system. The application note begins with recommended termination techniques for clock generators. Subsequently, power supply filtering and bypassing is discussed. Finally, the application note provides some recommendations on board layout.

標(biāo)簽： Semiconductor application generators PLL-based

上傳時(shí)間： 2013-12-20

上傳用戶：水中浮云
02 calgary PhD A Java-Based Wireless Framework for Location-Based Services Applications.pdf

資料->【E】光盤論文->【E1】斯坦福博士論文->02 calgary PhD A Java-Based Wireless Framework for Location-Based Services Applications.pdf

標(biāo)簽： Location-Based Applications Java-Based Framework

上傳時(shí)間： 2013-07-02

上傳用戶：亞亞娟娟123
FPGA-based high-order FIR filter design

FPGA-based high-order FIR filter design

標(biāo)簽： FPGA-based high-order filter design

上傳時(shí)間： 2013-08-06

上傳用戶：sssnaxie
Digital Down Converter Design based on FPGA

Digital Down Converter Design based on FPGA.

標(biāo)簽： Converter Digital Design based

上傳時(shí)間： 2013-08-13

上傳用戶：CSUSheep
fpga based jpge 壓縮算法

fpga based jpge 壓縮算法，性能不錯(cuò)，

標(biāo)簽： based fpga jpge 壓縮算法

上傳時(shí)間： 2013-08-14

上傳用戶：a471778

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CLock-based

There are many different (and often confusing) terms associated with CLock-based devices. This appl

Clock based on the VHDL design language, the revised time alarm can be set up

基于AVR單片機(jī)Mega16的電子時(shí)鐘設(shè)計(jì)

pic16f8 based clock, it display the time on the TV display. This include source code and sch

Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range

Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides

02 calgary PhD A Java-Based Wireless Framework for Location-Based Services Applications.pdf

FPGA-based high-order FIR filter design

Digital Down Converter Design based on FPGA

fpga based jpge 壓縮算法