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CODING-Events

  • Input Signal Rise and Fall Tim

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.

    標(biāo)簽: Signal Input Fall Rise

    上傳時(shí)間: 2013-10-23

    上傳用戶:copu

  • 介紹C16x系列微控制器的輸入信號(hào)升降時(shí)序圖及特性

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.

    標(biāo)簽: C16x 微控制器 輸入信號(hào) 時(shí)序圖

    上傳時(shí)間: 2014-04-02

    上傳用戶:han_zh

  • 基于ADSP-BF561 的數(shù)字?jǐn)z像系統(tǒng)設(shè)計(jì)

    基于ADSP-BF561的數(shù)字?jǐn)z像系統(tǒng)設(shè)計(jì)Design of Digital Video Camera System Based on Digital Signal ProcessorADSP-BF561(浙江大學(xué) 信息與通信工程研究所,浙江 杭州 310027) 馬海杰, 劉云海摘要:介紹了基于ADI雙核的數(shù)字信號(hào)處理芯片ADSP-BF561 的數(shù)字?jǐn)z像系統(tǒng)實(shí)現(xiàn)方案。系統(tǒng)包括硬件和軟件兩部分,硬件主要有ADSP-BF561及其外圍電路、音視頻模數(shù)/數(shù)模轉(zhuǎn)換、CF卡/微硬盤接口等部分。軟件主要有操作系統(tǒng)及音視頻編解碼算法等部分。關(guān)鍵詞:ADSP-BF561 ;數(shù)字?jǐn)z像機(jī);微硬盤;MPEG-4;A/D;D/A中圖分類號(hào):TN948.41文獻(xiàn)標(biāo)識(shí)碼:AAbstract: An implementation of digital video camera system based on ADI dual core digital signal processor ADSP-BF561 is introduced. The system can be divided into two parts——hardware and software design. The hardware design includes ADSP-BF561 and perpheral apparatus, A/D,D/A, CF card or Microdrive and so on. The software includes operating system , audio and video coding algorithm.Key words: ADSP-BF561; digital video camera; microdrive; MPEG-4;A/D;D/A

    標(biāo)簽: ADSP-BF 561 數(shù)字?jǐn)z像 系統(tǒng)設(shè)計(jì)

    上傳時(shí)間: 2013-11-10

    上傳用戶:yl1140vista

  • Actel HDL Coding

    叫你如何擁有良好的編碼風(fēng)格

    標(biāo)簽: Coding Actel HDL

    上傳時(shí)間: 2013-11-06

    上傳用戶:yt1993410

  • H.264碼流結(jié)構(gòu)解析

    MPEG(Moving Picture Experts Group)和VCEG(Video Coding Experts Group)已經(jīng)聯(lián)合開發(fā)了一個(gè)比早期研發(fā)的MPEG 和H.263 性能更好的視頻壓縮編碼標(biāo)準(zhǔn),這就是被命名為AVC(Advanced Video Coding),也被稱為ITU-T H.264 建議和MPEG-4 的第10 部分的標(biāo)準(zhǔn),簡稱為H.264/AVC 或H.264。這個(gè)國際標(biāo)準(zhǔn)已經(jīng)與2003 年3 月正式被ITU-T 所通過并在國際上正式頒布。為適應(yīng)高清視頻壓縮的需求,2004 年又增加了FRExt 部分;為適應(yīng)不同碼率及質(zhì)量的需求,2006 年又增加了可伸縮編碼 SVC。

    標(biāo)簽: 264 碼流

    上傳時(shí)間: 2013-11-19

    上傳用戶:dancnc

  • STBC系統(tǒng)在非同分布Nakagami信道下性能評(píng)估

    摘  要: 針對(duì)非同分布的Nakagami信道,基于矩生成函數(shù)MGF(Moment Generation Function)的分析方法,提出正交空時(shí)分組碼系統(tǒng)STBC(Space-Time Block Coding)的一種快速性能評(píng)估算法,不需要涉及超幾何函數(shù)積分運(yùn)算,可在中高信噪比時(shí),快速準(zhǔn)確地估計(jì)STBC系統(tǒng)的符號(hào)錯(cuò)誤概率性能。在平坦瑞利衰落信道下的計(jì)算機(jī)仿真表明,該算法與已有的STBC系統(tǒng)的近似估計(jì)算法相比,具有較優(yōu)的性能。      關(guān)鍵詞: 正交空時(shí)分組碼; MIMO; MGF; 誤符號(hào)率  

    標(biāo)簽: Nakagami STBC 分布

    上傳時(shí)間: 2014-12-29

    上傳用戶:如果你也聽說

  • 克服了正交頻分復(fù)用(OFDM)和IEEE 1901.2智能電網(wǎng)通信的挑戰(zhàn)

    Abstract: While many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.

    標(biāo)簽: 1901.2 OFDM IEEE 正交頻分復(fù)用

    上傳時(shí)間: 2013-10-18

    上傳用戶:myworkpost

  • Actel HDL Coding

    叫你如何擁有良好的編碼風(fēng)格

    標(biāo)簽: Coding Actel HDL

    上傳時(shí)間: 2014-01-04

    上傳用戶:s藍(lán)莓汁

  • Verilog編碼中的非阻塞性賦值

      One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions

    標(biāo)簽: Verilog 編碼 非阻塞性賦值

    上傳時(shí)間: 2013-11-01

    上傳用戶:xzt

  • Guide to HDL Coding Styles for Synthesis

    這篇文章討論了不同HDL代碼的編寫方式,對(duì)綜合結(jié)果的影響。閱讀本文對(duì)深入了解綜合工具和提高HDL的編寫水平有不少幫助,原文時(shí)針對(duì)Synopsys的綜合軟件論述的,但對(duì)所有綜合軟件,都有普遍的借鑒意義  

    標(biāo)簽: Synthesis Coding Styles Guide

    上傳時(shí)間: 2014-01-11

    上傳用戶:亞亞娟娟123

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