本文詳細(xì)分析了COOLRUNNER系列CPLD的結(jié)構(gòu),特點(diǎn)及功能,使用VHDL語(yǔ)言實(shí)現(xiàn)數(shù)字邏輯,實(shí)現(xiàn)了水下沖擊波記錄儀電路的數(shù)字電路部分.
標(biāo)簽： COOLRUNNER CPLD
上傳時(shí)間： 2013-08-26
上傳用戶(hù)：亞亞娟娟123
描述了用CoolRunner CPLD實(shí)現(xiàn)mp3 player的一種方法，值得學(xué)習(xí)
標(biāo)簽： CoolRunner player CPLD mp3
上傳時(shí)間： 2013-08-28
上傳用戶(hù)：chenhr
Interface 8051 to Coolrunner CPLD(Xilinx App)
標(biāo)簽： Coolrunner Interface Xilinx 8051
上傳時(shí)間： 2013-09-05
上傳用戶(hù)：bcjtao
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標(biāo)簽： CoolRunner-II XAPP CPLD 380
上傳時(shí)間： 2013-10-26
上傳用戶(hù)：kiklkook
There are many manufacturers of dot matrix LCD modules. However, most of these displaysare similar. They all have on-board controllers and drivers capable of displaying alpha numericsand a wide variety of other symbols (including Japanese "Katakana" characters). The internaloperation of LCD controller devices is determined by signals sent from a central processing unit(in this case, a CoolRunner-II CPLD).
標(biāo)簽： CoolRunner-II XAPP 904 LCD
上傳時(shí)間： 2013-12-17
上傳用戶(hù)：haiya2000
Interface 8051 to Coolrunner CPLD(Xilinx App)
標(biāo)簽： Coolrunner Interface Xilinx 8051
上傳時(shí)間： 2014-01-09
上傳用戶(hù)：sardinescn
描述了用CoolRunner CPLD實(shí)現(xiàn)mp3 player的一種方法，值得學(xué)習(xí)
標(biāo)簽： CoolRunner player CPLD mp3
上傳時(shí)間： 2015-12-10
上傳用戶(hù)：skhlm
本文詳細(xì)分析了COOLRUNNER系列CPLD的結(jié)構(gòu),特點(diǎn)及功能,使用VHDL語(yǔ)言實(shí)現(xiàn)數(shù)字邏輯,實(shí)現(xiàn)了水下沖擊波記錄儀電路的數(shù)字電路部分.
標(biāo)簽： COOLRUNNER CPLD VHDL 分
上傳時(shí)間： 2013-12-18
上傳用戶(hù)：shawvi
Xilinx COOLRUNNER-XPLA3 FPGA，元器件庫(kù)
標(biāo)簽： COOLRUNNER-XPLA Xilinx FPGA 元件庫(kù)
上傳時(shí)間： 2019-01-03
上傳用戶(hù)：mingrw
The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上傳時(shí)間： 2013-11-03
上傳用戶(hù)：1037540470
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