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CORE-Generato

Implements a 16550/16750 UART core

Implements a 16550/16750 UART core

標(biāo)簽： Implements 16550 16750 UART

上傳時(shí)間： 2017-06-25

上傳用戶(hù)：咔樂(lè)塢
Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit -

Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added

標(biāo)簽： Consecutive Description AES Features

上傳時(shí)間： 2017-06-25

上傳用戶(hù)：talenthn
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

標(biāo)簽： configurable controller universal adaptive

上傳時(shí)間： 2017-06-25

上傳用戶(hù)：皇族傳媒
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

標(biāo)簽： Tensilica OpenCores interface the

上傳時(shí)間： 2013-12-21

上傳用戶(hù)：gonuiln
avr core porocesssor vhdl source code

avr core porocesssor vhdl source code

標(biāo)簽： porocesssor source core code

上傳時(shí)間： 2017-06-26

上傳用戶(hù)：王慶才
another avr core porocesssor vhdl source code

another avr core porocesssor vhdl source code

標(biāo)簽： porocesssor another source core

上傳時(shí)間： 2013-12-13

上傳用戶(hù)：sammi
8051 mega core porocesssor vhdl source code

8051 mega core porocesssor vhdl source code

標(biāo)簽： porocesssor source 8051 mega

上傳時(shí)間： 2013-12-19

上傳用戶(hù)：diets
another 8051 core porocesssor vhdl source code

another 8051 core porocesssor vhdl source code

標(biāo)簽： porocesssor another source 8051

上傳時(shí)間： 2014-01-25

上傳用戶(hù)：牧羊人8920
Quartus中實(shí)現(xiàn)的DDS 使用的是altera提供的IP core

Quartus中實(shí)現(xiàn)的DDS 使用的是altera提供的IP core

標(biāo)簽： Quartus altera core DDS

上傳時(shí)間： 2017-06-27

上傳用戶(hù)：Breathe0125
Verilog for SPI Core source code

Verilog for SPI Core source code

標(biāo)簽： Verilog source Core code

上傳時(shí)間： 2014-01-01

上傳用戶(hù)：Shaikh

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