ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are Changed by an equal amount. It is usually expressed in LSBs.
上傳時間： 2013-11-12
上傳用戶：pans0ul
鎖定放大是微弱信號檢測的重要手段。基于相關檢測理論，利用開關電容的開關實現鎖定放大器中乘法器的功能，提出開關電容和積分器相結合以實現相關檢測的方法，并設計出一種鎖定放大器。該鎖定放大器將微弱信號轉化為與之相關的方波，通過后續電路得到正比于被測信號的直流電平，為后續采集處理提供方便。測量數據表明鎖定放大器前級可將10-6 A的電流轉換為10-1 V的電壓，后級通過帶通濾波器級聯可將信號放大1×105倍。該方法在降低噪聲的同時，可對微弱信號進行放大，線性度較高、穩定性較好。 Abstract: Lock-in Amplifying（LIA）is one of important means for weak signal detection. Based on cross-correlation detection theory， switch in the swithched capacitor was used as multiplier of LIA， and a new method of correlation detection was proposed combining swithched capacitor with integrator. A kind of LIA was designed which can convert the weak signal to square-wave， then DC proportional to measured signal was obtained through follow-up conditioning circuit， providing convenience for signal acquisition and processing. The measured data shows that the electric current（10-6 A） can be Changed into voltage（10-1 V） by LIA， and the signal is magnified 1×105 times by cascade band-pass filter. The noise is suppressed and the weak signal is amplified. It has the advantages of good linearity and stability.
上傳時間： 2013-11-29
上傳用戶：黑漆漆
針對材料試驗機等設備中要求測量或控制材料拉伸或壓縮的位移，一般采用光電軸角編碼器檢測位置信號，輸出正交編碼脈沖信號。若采用其他方法檢測位置信號，必然導致電路設計復雜，可靠性降低。因此，提出一種基于LS7266R1的電子式萬能材料試驗機設計方案。給出了試驗機中的控制器工作原理，LS7266R1與單片機的接口硬件設計，以及主程序軟件流程圖。巧妙地把力量傳感器，位移傳感器等機械運動狀態的壓力或拉力以及位置坐標，變成了電壓信號和電脈沖數字信號，供A/D測量和LS7266R1計數，從而實現了獨立完成材料試驗控制或通過PC機串口命令完成材料試驗控制。 Abstract: Aiming at the requirement that the displacement of the tension and compression always be tested and controlled in the equipement such as material testing machine. The position signal was tested by photoelectric axial angle coder. Therefore， the paper proposes the design of electronic universal testing machine design based on LS7266R1. If the position signal detected by other methods， will inevitably lead to the circuit design complexity， reliability decreased. The work theory of the controller， the hardware interface design between LS7266R1 and single chip， and the flow chart of main program， are presented in this paper. The signal of the compression or tension power and displacement at working， which tested by power sensor and displacement sensor especially， is Changed into electric voltage and electric pulse numerical signals. And these signals can be tested by A/D and counted by LS7266R1. Finally the test of the material properties can be controlled by itself， or controlled by the COM command of PC.
上傳時間： 2013-11-02
上傳用戶：yl1140vista
將現行的供暖計費方式由按建筑面積計費變為按消耗的熱能計費是供暖計費方式發展趨勢，為了滿足這一計費方式變化的需要，設計了基于IC卡的預付費式新型供暖計費系統，通過測量用戶采暖系統進出口的溫度和流量，計算用戶消耗的熱能，利用IC卡記錄用戶預付費的金額和當年熱能的單價，根據熱能消耗和當年熱能的單價計算用戶采暖費，根據實際發生的供暖費用和預付費金額控制供暖的開停，這一計費方式的變化使供暖計費更趨合理。 Abstract: It is trend that the mode of heat charging is Changed from billing by building area to by thermal energy. In order to meet the needs of heat charging mode changing， a new system of heat charging based on IC card is proposed. The user?蒺s energy consumption is calculated by measuring the user inlet and outlet temperature and flow，using the IC card to record the prepaid amount and the current price of heat. The user?蒺s heating costs is calculated according to energy consumption and current price， according to actual heating costs and prepaid amount，the system controls the heating opening or stopping. It is more reasonable that calculated heating costs by user heat consumption
上傳時間： 2013-10-14
上傳用戶：大融融rr
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be Changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2013-10-15
上傳用戶：euroford
FPGAs have Changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標簽： Methodology Design Reuse FPGA
上傳時間： 2013-10-23
上傳用戶：旗魚旗魚
We all know the benefits of using FieldProgrammable Gate Arrays (FPGAs): no NRE, nominimum order quantities, and faster time-tomarket.In an ideal world, designs would never needto be Changed because of design errors, but we allknow that sometimes this is necessary.
上傳時間： 2013-11-04
上傳用戶：leixinzhuo
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be Changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2014-11-26
上傳用戶：erkuizhang
FPGAs have Changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標簽： Methodology Design Reuse FPGA
上傳時間： 2013-11-01
上傳用戶：shawvi
Filename: main.c * Description: A simple test program for the CRC implementations. * Notes: To test a different CRC standard, modify crc.h. * * * Copyright (c) 2000 by Michael Barr. This software is placed into * the public domain and may be used for any purpose. However, this * notice must not be Changed or removed and no warranty is either * expressed or implied by its publication or distribution.
標簽： test implementations Description Filename
上傳時間： 2015-02-02
上傳用戶：leehom61
