The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed
to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6
as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up
the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are
ready for data operations
This example describes how to use the ADC and DMA to transfer continuously
converted data from ADC to a data buffer.
The ADC is configured to converts continuously ADC channel14.
Each time an end of conversion occurs the DMA transfers, in circular mode, the
converted data from ADC1 DR register to the ADC_ConvertedValue variable.
The ADC1 clock is set to 14 MHz.
SimpliciTI™ -1.0.4.exe for CC2430
SimpliciTI is a simple low-power RF network protocol aimed at small (<256) RF networks. Such networks typically contain battery operated devices which require long battery life, low data rate and low duty cycle and have a limited number of nodes talking directly to each other or through an access point or range extenders. Access point and range extenders are not required but provide extra functionality such as store and forward messages. With SimpliciTI the MCU resource requirements are minimal which results in the low system cost.
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp
terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any
synthesised using current synthesis tools.
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
300 km 傳輸線和功率補償仿真
The circuit below represents an equivalent power system feeding a 300 km transmission line. The line is compensated by a shunt inductor at its receiving end. A circuit breaker allows energizing and de-energizing of the line. To simplify matters, only one of the three phases is represented. The parameters shown in the figure are typical of a 735 kV power system.
The C++ standard library provides a set of common classes and interfaces that greatly extend the core C++ language. The library, however, is not self-explanatory. To make full use of its components - and to benefit from their power - you need a resource that does far more than list the classes and their functions.
Computtional Fluid Dynamics (CFD)
steady 1-Dimensional convection and diffusion
using central differencing, upwind differencing,
hybrid differencing and power law schemes,
programmed in MATLAB
sql equipment management system for the Institute of Laboratory office automation management system an important part of it can lend to the return of the equipment scrapped and a new standardized management, thereby increasing efficiency and avoiding waste of resources.
background database using Access, prospects of development tools using Visual Basic.
The system uses ADO data access technology, and each database table and operation of the field to the type of package, which succeeded in object-oriented programming thinking applied to the database application design.
