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Controller

  • PCA9541 2 to 1 I2C-bus master

    The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe Controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.

    標簽: master C-bus 9541 PCA

    上傳時間: 2013-10-09

    上傳用戶:3294322651

  • TJA1042 High-speed CAN transce

    The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol Controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicroController with) a CAN protocol Controller.

    標簽: High-speed transce 1042 TJA

    上傳時間: 2014-12-28

    上傳用戶:氣溫達上千萬的

  • TJA1051 High-speed CAN transce

    The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol Controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicroController with) a CAN protocol Controller.

    標簽: High-speed transce 1051 TJA

    上傳時間: 2013-10-17

    上傳用戶:jisujeke

  • 3-V TO 5.5-V MULTICHANNEL RS-2

    The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication Controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.

    標簽: MULTICHANNEL 5.5 TO RS

    上傳時間: 2013-10-19

    上傳用戶:ddddddd

  • 基于8086 CPU 的單芯片計算機系統的設計

    本文依據集成電路設計方法學,探討了一種基于標準Intel 8086 微處理器的單芯片計算機平臺的架構。研究了其與SDRAM,8255 并行接口等外圍IP 的集成,并在對AMBA協議和8086 CPU分析的基礎上,采用遵從AMBA傳輸協議的系統總線代替傳統的8086 CPU三總線結構,搭建了基于8086 IP 軟核的單芯片計算機系統,并實現了FPGA 功能演示。關鍵詞:微處理器; SoC;單芯片計算機;AMBA 協議 Design of 8086 CPU Based Computer-on-a-chip System(School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China)Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM Controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification

    標簽: 8086 CPU 單芯片 計算機系統

    上傳時間: 2013-12-27

    上傳用戶:kernor

  • 基于單片機的步進電機開環控制系統

    基于單片機的步進電機開環控制系統:通過ATMEL89C51單片機對步進電機進行控制,主要介紹了步進電機控制器、驅動電路和LED顯示電路的設計,實現了步進電機的開環控制。在步進電機控制器的設計中,重點闡述了脈沖產生電路以及對速度的控制。該系統具有成本低、控制方便的特點。關鍵詞: 單片機; 步進電機; 開環控制 Abstract: The design using ATMEL89C51 single chip to control the step2motor with its Controller, driving circuit and LED disp lay circuit to realize step motor open2loop controlwere introduced. For the Controller in this design,the circuit to p roduce pulse and the speed controlwere expatiated emphatically. This system possesses features of lower cost, easier control.Key words: single ch ip; step2motor; open2loop con trol

    標簽: 單片機 步進電機 開環 控制系統

    上傳時間: 2013-10-13

    上傳用戶:cicizoe

  • 基于單片機的除塵控制器的設計

    基于單片機的除塵控制器的設計:介紹通用控制儀的硬件組成和軟件設計,闡述了系統的性能指標和功能特點。該產品功能完善,可靠性高,具有很好的應用前景。關鍵詞: 除塵器;通用控制儀;單片機;系統設計 Abstract: The hardware structure and the software design are introduced in this paper, and the performance index and the features of the system are expounded. It has comp rehensive functions, high reliability and good app lication.Key words: dust catcher; universal Controller; microController; system design

    標簽: 單片機 除塵 控制器

    上傳時間: 2013-11-16

    上傳用戶:ming52900

  • 可編程中斷控制器82C59A-2

    82C59A-2是為簡化微處理機系統中斷接口而實現的LSI外圍芯片。也叫做PIC(Programmable Interrupt Controller)。是高性能高速度芯片。在多級優先級中斷系統內82C59A-1402已經把CPU從對任務的輪詢中解救出來。PCI可由軟件進行控制,使用于各種不同的環境,聯級可接受8~64個中斷輸入。 管腳與NMOS8259A-2兼容單片8級優先級,級聯可擴64級多種可編程中斷方式各自專用的請求屏蔽能力與Intel系列機兼容全部采用靜態設計低功耗5V的電源供電。

    標簽: 82 59 可編程 中斷控制器

    上傳時間: 2013-10-30

    上傳用戶:zhliu007

  • 基于單片機控制的二氧化碳濃度測試計

    基于單片機控制的二氧化碳濃度測試計:基于CDM4161二氧化碳氣體濃度測試模塊以及ATtiny26單片機,提出了一種二氧化碳濃度測試計的設計方案。該方案具有硬件電路簡單、成本低、可靠性高、測量準確等優點,具有較高的實用價值。 Abstract: Abstract:A desigh scheme of CO2 concentration meter based on CDM4161carbon dioxide concentration test module and ATtiny26micro-Controller is presented in this paper.The design scheme features simple hardware circuit,low-cost,high reli-ability,accurate measurement and it has a high practical value.

    標簽: 單片機控制 二氧化碳 測試

    上傳時間: 2013-11-14

    上傳用戶:zjwangyichao

  • MPC106 PCI橋/存儲器控制器硬件規范說明

    The Motorola MPC106 PCI bridge/memory Controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory ControllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29

    標簽: MPC 106 PCI 存儲器

    上傳時間: 2013-11-04

    上傳用戶:as275944189

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