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簡易頻率計設計

本實驗要求設計一個簡易的頻率計，實現對標準的方波信號進行頻率測量，并把測量的結果送到8 位的數碼管顯示，所要求測量范圍是1Hz~99999999Hz。整個設計的基本原理就是對1 秒鐘之內輸入的方波進行計數，把所得數據保存在計數器里，經過譯碼器處理之后，然后送往數碼管顯示。這里采用的方案是在采樣時鐘的上升沿開始計數，然后在下一個上升沿把計數器里的數據送往數碼管，并且把計數器清零，讓其重新計數。整個方案的實現主要分為四個模塊：時鐘分頻(clk_div)模塊、計數器模塊(Counter)、譯碼器模塊(seg8)、掃描輸出(saomiao)模塊

標簽： 頻率計設

上傳時間： 2013-11-20

上傳用戶：avensy
24c01a的讀寫程序

#include <at24c01a.h>/*************************************************向24C01A寫入一個字節輸入：E2ROM地址，字節數據******************************************************/void write24c01a(uchar uadd_1,uchar udata_1){sendbyte=0xa0;start();send(sendbyte);if (!ack())continue;send(uadd_1);if (!ack())continue;send(udata_1)if (!ack())continue;stop();}/**********************************發送開始*****************************************/void start(void){a_scl=1;a_sda=1;a_sda=0;a_scl=0;a_scl=1;}/********************************************發送停止*******************************************/void stop(void){a_scl=0;a_sda=0;a_scl=1;a_sda=1;} /*********************************************發送反饋************************************************/bit ack(void){int a_acka_scl=0;a_scl=0;a_scl=0;a_scl=1;a_ack=a_sda;a_scl=0;return(a_ack)}/**************************************發送無反饋********************************************/bit noack(void){int a_ack;a_scl=1;a_scl=1;a_scl=0;}/*******************************************發送****************************************************/void send(uchar undata){uchar i;sendbyte=undatafor(i=8;i>0;i--){a_sda=sendbyte7;a_scl=0;a_scl=1;sendbyte=sendbyte<<1}}/********************************************接受****************************************************/ void receive(void){int i;uchar data;for(i=8;i>0;i--){ a_scl=1;receivebyte7=a_sda;a_scl=0;receivebyte=receivebyte>>1}receivedata=receivebyte;}/********************************************向 24c01a讀一個字節；輸入：EEROM地址；輸出：EEROM數據；********************************************/void read24c01a(uchar Counter){receivebyte=0xa1;start();send(receivebyte);if (!ack())continue;send(Counter);if (!ack())continue;receive()noack();stop();}

標簽： 24c01a 讀寫程序

上傳時間： 2013-12-23

上傳用戶：wxhwjf
單片機系統“PC”失控的軟件措施

單片機系統“PC”失控的軟件措施Software Measure of GettingO uto fC ontrolfo r“PC"in S ingleC hipC omputerS ystem謐加春王曉基雷小華(江西理工大學機電工程學院，贛州 34 10 00)摘要單片機系統在實際工業現場中可能遇到各種干擾和自身的隨機性故障。現場惡劣的環境有可能使計算機系統發生異常，計算機程序指針“PC”失控就是常見的故障之一，如果發生“PC”失控，將導致CPI工作混亂，釀成嚴重的事故。研究了“PC”失控的原因，并指出軟件抗干擾的幾種方法，有效保證單片機系統的正常工作。關鍵詞單片機“PC”失控抗干擾Abstract Inp racticalin dustrialfi elds,th ereis v ariousin terferencea fectingo perationo fsi nglec hipc omputersy stemsa ndt hec omputersy stems。fac噸random faults飾themselves. It is very common that the severe environment makes the computer systems abnormal. The program Counter "PC"gettingo utof co ntorlis on eo fth ec ommonfa ults.If th isoc curs,C PUw ouldb eru nningo utof or deran din torducesse riousan cient.T hec ausesof " PC"geting out of control， studied in this paper and some Countermeasures of anti-interference師software are given to ensure single chip computer systemworking properly.Keywords Single。飾computer Porgramc ounter"P C" Anti-interfeernc 在設計和開發單片機系統時，一般難以周全地預計單片機系統在實際工業現場中可能遇到的各種干擾和自身的隨機性故障。因此，除了采取防止和抑制干擾的各項措施外，還應該借助于軟件措施克服某些干擾，系統還應具備迅速自行恢復的能力。本文介紹的應對單片機系統PC失控的軟件措施，設計靈活，節省硬件資源，能保證測控系統長期可靠地運行。MC S- 5 1單片機以其優良的性能價格比大量應用于工業現場測試和控制領域。但是，現場惡劣的環境有可能使計算機系統發生異常，計算機程序指針PC失控就是常見的故障之一，一旦發生PC“走飛”，計算機系統就會出現工作混亂，釀成嚴重的事故。為了在 CP 失控時盡量減少由此帶來的不利影響，并盡快使系統恢復正常，需要采取一定的軟件措施和硬件措施。常見的硬件措施有“看門狗”電路。軟件措施設置的前提條件是:①在干擾作用下，微機系統硬件部分不會受到任何損壞，或者損壞部分設置有監測狀態可供查詢;②程序區不會受到干擾侵害。單片機系統的程序和表格以及重要的參數均設置在ROM區，不會因干擾的侵人而改變;③ RAM區中的重要數據不會被破壞，或者雖然被破壞，但是可以重新建立。

標簽： 單片機系統軟件

上傳時間： 2013-11-02

上傳用戶：bhqrd30
UHF讀寫器設計中的FM0解碼技術

針對UHF讀寫器設計中，在符合EPC Gen2標準的情況下，對標簽返回的高速數據進行正確解碼以達到正確讀取標簽的要求，提出了一種新的在ARM平臺下采用邊沿捕獲統計定時器數判斷數據的方法，并對FM0編碼進行解碼。與傳統的使用定時器定時采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時器定時誤差累積的影響；可以將捕獲定時器數中斷與數據判斷解碼相對分隔開，使得中斷對解碼影響很小，實現捕獲與解碼的同步。通過實驗表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標簽的時間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer Counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.

標簽： UHF FM0 讀寫器解碼技術

上傳時間： 2013-11-10

上傳用戶：liufei
lcd計數顯示程序

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end Counter;

標簽： lcd 計數顯示程序

上傳時間： 2013-10-30

上傳用戶：wqxstar
基于（英蓓特）STM32V100的看門狗程序

This example shows how to update at regulate period the WWDG Counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG Counter reaches 40h the EWI is generated and in the WWDGISR the Counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG Counter not updated). As result, when theWWDG Counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG Counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).

標簽： V100 STM 100 32V

上傳時間： 2013-11-11

上傳用戶：gundamwzc
This design is a universal register which can be used as a straightforward storage register, a bi-di

This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up Counter and a down Counter.

標簽： register straightforward universal storage

上傳時間： 2013-12-28

上傳用戶：努力努力再努力
這是我自己編寫的三分頻

這是我自己編寫的三分頻，也就是奇數分頻，占空比為1：1，當然如果需要其它奇數分頻，只要將程序里面的N和Counter修改即可

標簽： 編寫三分頻

上傳時間： 2015-08-06

上傳用戶：我們的船長
Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple

Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple Counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.

標簽： Spartan drives This perphrials

上傳時間： 2014-05-29

上傳用戶：SimonQQ
This example provides a description of how to use a DMA channel to transfer a word data buffer fro

This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data buffer stored as constant in the Flash memory to another buffer in the RAM memory. The received data are stored in the DST_Buffer. The DMA channel transfer complete interrupt is enabled to generate an interrupt at the end of the buffer transfer. As soon as the transfer is completed an interrupt is generated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data Counter is stored before and after the transfer to show that all data has been transfered. TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED

標簽： description provides transfer example

上傳時間： 2016-04-24

上傳用戶：ecooo