Full support for extended regular expressions (those with intersection and complement); Support for some kinds of Cycles in grammar; DFA-based operation; Unicode support; C++ only, requires a modern compiler; Lexical analyzers can be configured to get symbols from any input class (built-in support for std::istream, std::wistream and FILE *); Designed to work with Whale, but can work standalone or interface to other parsers.
This example program shows how to configure PCA Module 4 as a
watchdog timer. In this example, the watchdog is configured to
overflow after 0xFF00 clock Cycles.
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK
Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is
set at 50000 DCO/SMCLK Cycles. Default DCO frequency used for TACLK.
Durring the TA_0 ISR P5.1 is toggled and 50000 clock Cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 Cycles. CPU is normally off and
used only durring TA_ISR.
ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k
The algorith divides rows in to four equal groups. The rows are then used to from a distance graph which is then transformed into a matrix. girth of eight is maintained by avoiding six-Cycles in the graph construction
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write Cycles, 8-bit Memory Read/Write Cycles, DMA Cycles, and up to 32-bit Firmware memory read/write Cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Topics Practices:
Programming and Numerical Methods
Practice 1: Introduction to C
Practice 2: Cycles and functions
First part Cycles
Part Two: Roles
Practice 3 - Floating point arithmetic
Practice 4 - Search for roots of functions
Practice 5 - Numerical Integration
Practice 6 - Arrangements and matrices
Part One: Arrangements
Part II: Matrices
Practice 7 - Systems of linear equations
Practice 8 - Interpolation
Practice 9 - Algorithm Design Techniques
