關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
This paper investigates the design of joint frequency offset and carrier phase estimation of a multi-frequency time division multiple access (MF-TDMA) demodulator that is applied to a digital video broadcasting—return channel system via satellite (DVB-RCS). The proposed joint estimation algorithm is based on the interpolation technique for two correlation values in the frequency and phase domains. This simple interpolation technique can significantly improve frequency and phase resolution capabilities of the proposed technique without increasing the number of the correlation values. In addition, the overall block diagram of a digital communications receiver for DVB-RCS is presented, which was designed using the proposed estimation algorithms. Index Terms—Carrier phase estimation, DVB-RCS, frequency offset estimation, interpolation, joint estimation, MF-TDMA.
標簽： investigates estimation frequency carrier
上傳時間： 2015-12-30
上傳用戶：ls530720646
關于FPGA流水線設計的論文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na
上傳時間： 2013-09-03
上傳用戶：wl9454
本文依據集成電路設計方法學，探討了一種基于標準Intel 8086 微處理器的單芯片計算機平臺的架構。研究了其與SDRAM，8255 并行接口等外圍IP 的集成，并在對AMBA協議和8086 CPU分析的基礎上，采用遵從AMBA傳輸協議的系統總線代替傳統的8086 CPU三總線結構，搭建了基于8086 IP 軟核的單芯片計算機系統，并實現了FPGA 功能演示。關鍵詞：微處理器； SoC；單芯片計算機；AMBA 協議 Design of 8086 CPU Based Computer-on-a-chip System（School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China）Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification
上傳時間： 2013-12-27
上傳用戶：kernor
This book provides an overview of recent innovations and achievements in the broad areas of cyber-physical systems (CPS), including architecture, networking, systems, applications, security, and privacy. The book discusses various new CPS technologies from diverse aspects to enable higher level of innovation towards intelligent life. The book provides insight to the future integration, coordination and interaction between the physical world, the information world, and human beings. The book features contributions from renowned researchers and engineers, who discuss key issues from various perspectives, presenting opinions and recent CPS-related achievements.investigates how to advance the development of cyber-physical systems Provides a joint consideration of other newly emerged technologies and concepts in relation to CPS like cloud computing, big data, fog computing, and crowd sourcing Includes topics related to CPS such as architecture, system, networking, application, algorithm, security and privacy
上傳時間： 2019-04-21
上傳用戶：danyun
Abstract—In the future communication applications, users may obtain their messages that have different importance levels distributively from several available sources, such as distributed storage or even devices belonging to other users. This scenario is the best modeled by the multilevel diversity coding systems (MDCS). To achieve perfect (information-theoretic) secrecy against wiretap channels, this paper investigates the fundamental limits on the secure rate region of the asymmetric MDCS (AMDCS), which include the symmetric case as a special case. Threshold perfect secrecy is added to the AMDCS model. The eavesdropper may have access to any one but not more than one subset of the channels but know nothing about the sources, as long as the size of the subset is not above the security level. The question of whether superposition (source separation) coding is optimal for such an AMDCS with threshold perfect secrecy is answered. A class of secure AMDCS (S-AMDCS) with an arbitrary number of encoders is solved, and it is shown that linear codes are optimal for this class of instances. However, in contrast with the secure symmetric MDCS, superposition is shown to be not optimal for S-AMDCS in general. In addition, necessary conditions on the existence of a secrecy key are determined as a design guideline.
標簽： Fundamental Limits Secure Class on of
上傳時間： 2020-01-04
上傳用戶：kddlas
