-- M68008 Address DeCoder
-- Address DeCoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
The same two-stage DeCoder as above. However, when transforming the symbols prior to Viterbi decoding, the amplitude information is ignored and only the phase of the received symbol is employed in the metric computation stage.
encode.v The encoder
syndrome.v Syndrome generator in DeCoder
berlekamp.v Berlekamp algorithm in DeCoder
chien-search.v Chien search and Forney algorithm in DeCoder
decode.v The top module of the DeCoder
inverse.v Computes multiplication inverse of an Galois field element
test-bench.v The test fixture, and some brief notes on using the modules.
data-rom.v A simple data source for testing
run For those intelligence-challenged who can t run verilog
LGPL The license
