低密度校驗(yàn)碼（LDPC，Low Density Parity Check Code）是一種性能接近香農(nóng)極限的信道編碼，已被廣泛地采用到各種無線通信領(lǐng)域標(biāo)準(zhǔn)中，包括我國的數(shù)字電視地面?zhèn)鬏敇?biāo)準(zhǔn)、歐洲第二代衛(wèi)星數(shù)字視頻廣播標(biāo)準(zhǔn)（DVB-S2，Digital Video Broadcasting-Satellite 2）、IEEE 802.11n、IEEE 802.16e等。它是3G乃至將來4G通信系統(tǒng)中的核心技術(shù)之一。 當(dāng)今LDPC碼構(gòu)造的主流方向有兩個(gè)，分別是結(jié)合準(zhǔn)循環(huán)（QC，Quasi Cyclic）移位結(jié)構(gòu)的單次擴(kuò)展構(gòu)造和類似重復(fù)累積（RA，Repeat Accumulate）碼構(gòu)造。相應(yīng)地，主要的LDPC碼編碼算法有基于生成矩陣的算法和基于迭代譯碼的算法?；谏删仃嚨木幋a算法吞吐量高，但是需要較多的寄存器和ROM資源；基于迭代譯碼的編碼算法實(shí)現(xiàn)簡單，但是吞吐量不高，且不容易構(gòu)造高性能的好碼。 本文在研究了上述幾種碼構(gòu)造和編碼算法之后，結(jié)合編譯碼器綜合實(shí)現(xiàn)的復(fù)雜度考慮，提出了一種切實(shí)可行的基于二次擴(kuò)展（Dex，Duplex Expansion）的QC-LDPC碼構(gòu)造方法，以實(shí)現(xiàn)高吞吐量的LDPC碼收發(fā)端；并且充分利用該類碼校驗(yàn)矩陣準(zhǔn)循環(huán)移位結(jié)構(gòu)的特點(diǎn)，結(jié)合RU算法，提出了一種新編碼器的設(shè)計(jì)方案。 基于二次擴(kuò)展的QC-LDPC碼構(gòu)造方法，是通過對(duì)母矩陣先后進(jìn)行亂序擴(kuò)展（Pex，Permutation Expansion）和循環(huán)移位擴(kuò)展（CSEx，Cyclic Shift Expansion）實(shí)現(xiàn)的。在此基礎(chǔ)上，為了實(shí)現(xiàn)可變碼長、可變碼率，一般編譯碼器需同時(shí)支持多個(gè)亂序擴(kuò)展和循環(huán)移位擴(kuò)展的擴(kuò)展因子。本文所述二次擴(kuò)展構(gòu)造方法的特點(diǎn)在于，固定循環(huán)移位擴(kuò)展的擴(kuò)展因子大小不變，支持多個(gè)亂序擴(kuò)展的擴(kuò)展因子，使得譯碼器結(jié)構(gòu)得以精簡；構(gòu)造得到的碼字具有近似規(guī)則碼的結(jié)構(gòu)，便于硬件實(shí)現(xiàn)；（偽）隨機(jī)生成的循環(huán)移位系數(shù)能夠提高碼字的誤碼性能，是對(duì)硬件實(shí)現(xiàn)和誤碼性能的一種折中。 新編碼器在很大程度上考慮了資源的復(fù)用，使得實(shí)現(xiàn)復(fù)雜度近似與碼長成正比。考慮到吞吐量的要求，新編碼器結(jié)構(gòu)完全拋棄了RU算法中串行的前向替換（FS，F(xiàn)orward Substitution）模塊，同時(shí)簡化了流水線結(jié)構(gòu)，由原先RU算法的6級(jí)降低為4級(jí)；為了縮短編碼延時(shí)，設(shè)計(jì)時(shí)安排每一級(jí)流水線計(jì)算所需的時(shí)鐘數(shù)大致相同。 這種碼字構(gòu)造和編碼聯(lián)合設(shè)計(jì)方案具有以下優(yōu)勢：相比RU算法，新方案對(duì)可變碼長、可變碼率的支持更靈活，吞吐量也更大；相比基于生成矩陣的編碼算法，新方案節(jié)省了50％以上的寄存器和ROM資源，單位資源下的吞吐量更大；相比類似重復(fù)累積碼結(jié)構(gòu)的基于迭代譯碼的編碼算法，新方案使高性能LDPC碼的構(gòu)造更為方便。以上結(jié)果都在Xilinx Virtex II pro 70 FPGA上得到驗(yàn)證。 通過在實(shí)驗(yàn)板上實(shí)測表明，上述基于二次擴(kuò)展的QC-LDPC碼構(gòu)造和相應(yīng)的編碼方案能夠?qū)崿F(xiàn)高吞吐量LDPC碼收發(fā)端，在實(shí)際應(yīng)用中具有很高的價(jià)值。 目前，LDPC碼正向著非規(guī)則、自適應(yīng)、信源信道及調(diào)制聯(lián)合編碼方向發(fā)展?？鐚勇?lián)合編碼的構(gòu)造方法，及其對(duì)應(yīng)的編碼算法，也必將成為信道編碼理論未來的研究重點(diǎn)。
上傳時(shí)間： 2013-07-26
上傳用戶：qoovoop
介紹一種簡單射頻識(shí)別系統(tǒng)設(shè)計(jì)。該設(shè)計(jì)包括閱讀器、應(yīng)答器和線圈3部分。由單片機(jī)控制閱讀器向應(yīng)答器發(fā)射無線信號(hào)，并接收應(yīng)答器回送的信號(hào)，再通過分析回送信號(hào)識(shí)別物品。閱讀器和應(yīng)答器之間以半雙工通信方式通信。 Abstract: A simple design of radio frequency identification system is given in this paper.The design includes reader,responder and winding.Through MCU，signals are sent to responder from reader，then corresponding signals are sent back. According to the analysis of the signals sent back，the objects can be identified.Half-Duplex communication is adopted? between? reader? and? responder.
標(biāo)簽： 51單片機(jī) 無線識(shí)別 裝置
上傳時(shí)間： 2013-10-11
上傳用戶：plsee
基于幅移鍵控技術(shù)ASK（Amplitude-Shift Keying），以C8051F340單片機(jī)作為監(jiān)測終端控制器，C8051F330D單片機(jī)作為探測節(jié)點(diǎn)控制器，采用半雙工的通信方式，通過監(jiān)控終端和探測節(jié)點(diǎn)的無線收發(fā)電路，實(shí)現(xiàn)數(shù)據(jù)的雙向無線傳輸。收發(fā)電路采用直徑為0.8 mm的漆包線自行繞制成圓形空心線圈天線，天線直徑為（3.4±0.3）cm。試驗(yàn)表明，探測節(jié)點(diǎn)與監(jiān)測終端的通信距離為24 cm，通過橋接方式，節(jié)點(diǎn)收發(fā)功率為102 mW時(shí)，節(jié)點(diǎn)間的通信距離可達(dá)20 cm。與傳統(tǒng)無線收發(fā)模塊相比，該無線收發(fā)電路在受體積、功耗、成本限制的場合有廣闊的應(yīng)用前景。 Abstract: Based on ASK technology and with the C8051F340 and C8051F330D MCU as the controller， using half-Duplex communication mode， this paper achieves bi-directional data transfer. Transceiver circuit constituted by enameled wire which diameter is 0.8mm and wound into a diameter （3.4±0.3） cm circular hollow coil antenna. Tests show that the communication distance between detection and monitoring of the terminal is 24cm，the distance is up to 20cm between two nodes when using the manner of bridging and the node transceiver power is 102mW. Compared with the conventional wireless transceiver modules， the circuit has wide application prospect in small size， low cost and low power consumption and other characteristics.
標(biāo)簽： C8051F 單片機(jī) 無線收發(fā) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-19
上傳用戶：xz85592677
The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full Duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.
標(biāo)簽： 1700 MIIM LPC 以太網(wǎng)
上傳時(shí)間： 2013-11-09
上傳用戶：geshaowei
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half Duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標(biāo)簽： synchronous Emulating serial
上傳時(shí)間： 2014-01-31
上傳用戶：z1191176801
8051參考設(shè)計(jì)，與其他8051的免費(fèi)IP相比，文檔相對(duì)較全，Oregano System 提供 This is version 1.3 of the MC8051 IP core. September 2002: Oregano Systems - Design & Consulting GesmbH Change history: - Improved tb_mc8051_siu_sim.vhd to verify Duplex operation. - Corrected problem with Duplex operation in file mc8051_siu_rtl.vhd
上傳時(shí)間： 2014-12-28
上傳用戶：tb_6877751
AFDX（ Avionics Full Duplex Switch Ethernet）是空客公司首先提出的， 在商用以太網(wǎng)技術(shù)的基礎(chǔ)上，通過增加特殊功能來保證航空應(yīng)用的確定性和可靠性，是目前最先進(jìn)的機(jī)載通信網(wǎng)絡(luò)。文中針對(duì)航電設(shè)備與總線網(wǎng)絡(luò)通信出現(xiàn)的故障，設(shè)計(jì)了某型號(hào)飛機(jī)AFDX總線監(jiān)控器，該設(shè)備是一個(gè)便攜式工控機(jī)，通過擴(kuò)展AFDX總線接口卡，實(shí)時(shí)、高速、可靠的對(duì)總線上的數(shù)據(jù)進(jìn)行記錄、分析、顯示，并依照航電總線標(biāo)準(zhǔn)ICD（接口控制文件）庫進(jìn)行解析，快速準(zhǔn)確的定位故障，避免設(shè)備的無故障拆裝，提高維護(hù)效率。仿真實(shí)驗(yàn)表明：該監(jiān)控器可實(shí)時(shí)監(jiān)控航電AFDX 總線上的所有動(dòng)態(tài)信息，對(duì)信息的分析處理正確，能滿足設(shè)計(jì)需求。
上傳時(shí)間： 2013-10-17
上傳用戶：zyt
8051參考設(shè)計(jì)，與其他8051的免費(fèi)IP相比，文檔相對(duì)較全，Oregano System 提供 This is version 1.3 of the MC8051 IP core. September 2002: Oregano Systems - Design & Consulting GesmbH Change history: - Improved tb_mc8051_siu_sim.vhd to verify Duplex operation. - Corrected problem with Duplex operation in file mc8051_siu_rtl.vhd
上傳時(shí)間： 2013-11-06
上傳用戶：XLHrest
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
標(biāo)簽： 8226 Programmable Compatible In-System
上傳時(shí)間： 2015-06-27
上傳用戶：dianxin61
看n2實(shí)例 #Create a simulator object set ns [new Simulator] #Define different colors for data flows #$ns color 1 Blue #$ns color 2 Red #Open the nam trace file set nf [open out-1.nam w] $ns namtrace-all $nf set f0 [open out0.tr w] set f1 [open out1.tr w] #Define a finish procedure proc finish {} { global ns nf $ns flush-trace #Close the trace file close $nf #Execute nam on the trace file exit 0 } #Create four nodes set n0 [$ns node] set n1 [$ns node] set n2 [$ns node] set n3 [$ns node] #Create links between the nodes $ns Duplex-link $n0 $n2 1Mb 10ms
標(biāo)簽： simulator Simulator different Create
上傳時(shí)間： 2016-07-02
上傳用戶：wfl_yy
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