Building a RISC System in an FPGA
標(biāo)簽： Building System RISC FPGA
上傳時(shí)間： 2013-09-04
上傳用戶：朗朗乾坤
本設(shè)計(jì)的基本要求是以復(fù)雜可編程邏輯器件CPLD為基礎(chǔ)，通過在EDA系統(tǒng)軟件ispDesignExpert System 環(huán)境下進(jìn)行數(shù)字系統(tǒng)設(shè)計(jì)，熟練掌握該環(huán)境下的功能仿真，時(shí)間仿真，管腳鎖定和芯片下載。 本系統(tǒng)基本上比較全面的模擬了計(jì)數(shù)式數(shù)字頻率計(jì)，廣泛應(yīng)用于工業(yè)、民用等各個(gè)領(lǐng)域，具有一定的開發(fā)價(jià)值。
標(biāo)簽： ispDesignExpert System EDA 系統(tǒng)軟件
上傳時(shí)間： 2013-09-05
上傳用戶：文993
Allegro design guide \r\nAllegro design guide
標(biāo)簽： Allegro design guide
上傳時(shí)間： 2013-09-07
上傳用戶：mnacyf
System will automatically delete the directory
標(biāo)簽： automatically directory System delete
上傳時(shí)間： 2013-09-09
上傳用戶：toyoad
* DESCRIPTION: DDS design BY PLD DEVICES.\r\n *\r\n * AUTHOR: Sun Yu\r\n *\r\n * HISTORY: 12/06/2002 \r\n *
標(biāo)簽： DESCRIPTION DEVICES design DDS
上傳時(shí)間： 2013-09-09
上傳用戶：jokey075
protel99se pcb design
標(biāo)簽： protel design pcb 99
上傳時(shí)間： 2013-09-11
上傳用戶：dyctj
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時(shí)間： 2013-11-22
上傳用戶：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2014-12-23
上傳用戶：xinhaoshan2016
Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in
標(biāo)簽： Allegro-Design-Editor-Tutorial_ad e_tut
上傳時(shí)間： 2014-08-09
上傳用戶：龍飛艇
為得到性能優(yōu)良、符合實(shí)際工程的鎖相環(huán)頻率合成器，提出了一種以ADI的仿真工具ADIsimPLL為基礎(chǔ)，運(yùn)用ADS（Advanced Design System 2009）軟件的快速設(shè)計(jì)方法。采用此方法設(shè)計(jì)了頻率輸出為930~960 MHz的頻率合成器。結(jié)果表明該頻率合成器的鎖定時(shí)間、相位噪聲以及相位裕度等指標(biāo)均達(dá)到了設(shè)計(jì)目標(biāo)。
標(biāo)簽： 4111 ADF 鎖相環(huán) 頻率合成器
上傳時(shí)間： 2013-12-16
上傳用戶：萍水相逢
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