In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-23
上傳用戶：我干你啊
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上傳時間： 2013-11-20
上傳用戶：pzw421125
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標簽： Methodology Design Reuse FPGA
上傳時間： 2013-11-01
上傳用戶：shawvi
為了在CDMA系統(tǒng)中更好地應用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎上，設計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標簽： QDPSK CPLD 調(diào)制解調(diào) 電路設計
上傳時間： 2013-10-28
上傳用戶：jyycc
波長信號的解調(diào)是實現(xiàn)光纖光柵傳感網(wǎng)絡的關鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設計，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
標簽： FPGA 光纖光柵 解調(diào)系統(tǒng)
上傳時間： 2013-10-10
上傳用戶：zxc23456789
8051參考設計，與其他8051的免費IP相比，文檔相對較全，Oregano System 提供 This is version 1.3 of the MC8051 IP core. September 2002: Oregano Systems - Design & Consulting GesmbH Change history: - Improved tb_mc8051_siu_sim.vhd to verify duplex operation. - Corrected problem with duplex operation in file mc8051_siu_rtl.vhd
上傳時間： 2013-11-06
上傳用戶：XLHrest
The revolution of automation on factory floors is a key driver for the seemingly insatiable demand for higher productivity， lower total cost of ownership，and high safety. As a result， industrial applications drive an insatiable demand of higher data bandwidth and higher system-level performance. This white paper describes the trends and challenges seen by designers and how FPGAs enable solutions to meet their stringent design goals.
上傳時間： 2013-11-08
上傳用戶：yan2267246
主機氣缸油注油器說明書，Alpha Lubricator System Operation (ALCU) manual MC Engines。
標簽： Lubricator Operation Engines System
上傳時間： 2013-10-17
上傳用戶：ynzfm
Abstract: This application note explains how to design an intelligent lighting controller that senses and measures the ambient lightlevel with an ambient light sensor (ALS). Equipped with a real-time clock (RTC), the controller also knows when to turn lighting on oroff at specified times. The system presented in this document can be used to control all luminaires that are mains-supply operated.Controller software is also provided in hex format.
標簽： 智能照明控制器 測量 環(huán)境光線
上傳時間： 2013-11-18
上傳用戶：AbuGe
本程序集是Allen I. Holub所寫的《Compiler Design in C》一書的附隨軟件，其中有作者自己編寫的詞法分析和語法分析工具LeX，occs和LLama，該軟件包還包括一個顯示C語言分析過程的程序
上傳時間： 2014-01-08
上傳用戶：siguazgb
