struts-Exercise-taglib
標(biāo)簽： struts-Exercise-taglib
上傳時(shí)間： 2015-01-22
上傳用戶：tuilp1a
Beginning Java 2, SDK 1.4 Edition Exercise Code samples for this book
標(biāo)簽： Beginning Exercise Edition samples
上傳時(shí)間： 2013-12-13
上傳用戶：佳期如夢
a better book about learning C++,and have the programing code for the Exercise
標(biāo)簽： programing the learning Exercise
上傳時(shí)間： 2015-07-15
上傳用戶：gundamwzc
Script file for computer Exercise "BPSK".
標(biāo)簽： computer Exercise Script BPSK
上傳時(shí)間： 2015-08-07
上傳用戶：songnanhua
Random matrix theory - Exercise.
標(biāo)簽： Exercise Random matrix theory
上傳時(shí)間： 2013-12-13
上傳用戶：xiaoxiang
Lab 2 – Synthesizable MATLAB This lab Exercise will explore the effects that different MATLAB coding styles have on hardware. The lab has two parts, each of which begins with a short introduction. This lab Exercise is based on the simple MATLAB FIR filter model shown below:
標(biāo)簽： MATLAB Synthesizable different Exercise
上傳時(shí)間： 2015-09-28
上傳用戶：sammi
This getting started Exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.
標(biāo)簽： step-by-step transforming Exercise getting
上傳時(shí)間： 2014-01-17
上傳用戶：VRMMO
This lab Exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.
標(biāo)簽： fixed-point conversion introduce AccelDSP
上傳時(shí)間： 2015-09-28
上傳用戶：zxc23456789
This lab Exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each generator offers macro and micro-architecture selections that allow full customization of the generated model to the target application requirements.
標(biāo)簽： AccelWare generators introduce Exercise
上傳時(shí)間： 2013-12-16
上傳用戶：2467478207
This lab Exercise will cover the use of AccelDSP’s design exploration capabilities that include mapping variables to memory and unrolling loop and vector operations. You will learn how to create different hardware architectures without modifying the MATLAB source to explore different area/performance tradeoffs.
標(biāo)簽： capabilities exploration AccelDSP Exercise
上傳時(shí)間： 2014-12-22
上傳用戶：eclipse
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