Verilog and VHDL狀態機設計，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding
presented. Different methodologies will be compared using real-world examples.
synopsis的有限狀態機編碼方法的文檔。
針對synopsis的綜合環境，根據其綜合工具的特點說明安全可靠、速度適合的FSM編碼風格。
FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.
