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Features

MT8870D DTMF解碼芯片

Features• Complete DTMF Receiver• Low power consumption• Internal gain setting amplifier• Adjustable guard time• Central office quality• Power-down mode• Inhibit mode• Backward compatible withMT8870C/MT8870C-1Applications• Receiver system for British Telecom (BT) orCEPT Spec (MT8870D-1)• Paging systems• Repeater systems/mobile radio• Credit card systems• Remote control• Personal computers• Telephone answering machine

標簽： 8870D 8870 DTMF MT

上傳時間： 2013-11-20

上傳用戶：mpquest
LPC1769 LPC1768 LPC1767 LPC176

The LPC1769/68/67/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug Features and a higher level of support block integration.

標簽： LPC 1769 1768 1767

上傳時間： 2014-02-20

上傳用戶：13215175592
LPC1700以太網MIIM接口應用筆記

The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.

標簽： 1700 MIIM LPC 以太網

上傳時間： 2013-11-09

上傳用戶：geshaowei
CAT28LV64-64Kb CMOS并行EEPROM數據手

The CAT28LV64 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self−timed write cycle. Additionally, the CAT28LV64 Features hardware and software write protection.

標簽： EEPROM 64 CMOS CAT

上傳時間： 2013-11-16

上傳用戶：浩子GG
CAT25128－128Kb的SPI串行CMOS EEPRO

The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This Features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device Featuressoftware and hardware write protection, including partial as well as full array protection.

標簽： 25128 EEPRO CMOS CAT

上傳時間： 2013-11-15

上傳用戶：fklinran
FREERTOS的官方移植文檔

FeaturesThe following standard Features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples

標簽： FREERTOS 移植文檔

上傳時間： 2013-10-13

上傳用戶：13162218709
HCS12X系列存儲器配置操作指南

The HCS12X family is the successor to the HCS12family, with many additional Features. One new feature isthe increased memory available to the CPU and themethods available to access it. This document focuses onthe improved memory map configuration.

標簽： HCS 12X 12 存儲器

上傳時間： 2013-11-13

上傳用戶：王者A
開放式匯編器系統的設計

匯編器在微處理器的驗證和應用中舉足輕重，如何設計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統設計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發了一套匯編器系統，具有較高層次上的通用性和可移植性。【關鍵詞】指令集，CMDL，匯編器，開放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of Features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability

標簽： 開放式匯編器

上傳時間： 2013-10-10

上傳用戶：meiguiweishi
SJA1000 Stand-alone CAN contro

The Controller Area Network (CAN) is a serial, asynchronous, multi-master communication protocol forconnecting electronic control modules, sensors and actuators in automotive and industrial applications.With the SJA1000, Philips Semiconductors provides a stand-alone CAN controller which is more than a simpleeplacement of the PCA82C200.Attractive Features are implemented for a wide range of applications, supporting system optimization, diagnosisand maintenance.

標簽： Stand-alone contro 1000 SJA

上傳時間： 2013-11-18

上傳用戶：yxgi5
PCA9516 5channel I2C hub

The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and Features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.

標簽： 5channel 9516 PCA I2C

上傳時間： 2013-11-21

上傳用戶：q123321

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