library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end counter;
標(biāo)簽： lcd 計(jì)數(shù)顯示 程序
上傳時(shí)間： 2013-10-30
上傳用戶：wqxstar
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時(shí)間： 2013-10-31
上傳用戶：yy_cn
enter——選取或啟動(dòng) esc——放棄或取消 f1——啟動(dòng)在線幫助窗口 tab——啟動(dòng)浮動(dòng)圖件的屬性窗口 pgup——放大窗口顯示比例 pgdn——縮小窗口顯示比例 end——刷新屏幕 del——刪除點(diǎn)取的元件（1個(gè)） ctrl+del——刪除選取的元件（2個(gè)或2個(gè)以上） x+a——取消所有被選取圖件的選取狀態(tài) x——將浮動(dòng)圖件左右翻轉(zhuǎn) y——將浮動(dòng)圖件上下翻轉(zhuǎn) space——將浮動(dòng)圖件旋轉(zhuǎn)90度 crtl+ins——將選取圖件復(fù)制到編輯區(qū)里 shift+ins——將剪貼板里的圖件貼到編輯區(qū)里 shift+del——將選取圖件剪切放入剪貼板里 alt+backspace——恢復(fù)前一次的操作 ctrl+backspace——取消前一次的恢復(fù) crtl+g——跳轉(zhuǎn)到指定的位置 crtl+f——尋找指定的文字
上傳時(shí)間： 2013-11-01
上傳用戶：a296386173
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
A simple utility to split a concatenated vCard format file into separate files (IETF RFC 2426 - vCard MIME Directory Profile). It splits on the BEGIN:VCARD and END:VCARD tags. It was created to help import a Lotus Organizer export file into Palm Desktop
標(biāo)簽： concatenated separate utility simple
上傳時(shí)間： 2013-12-20
上傳用戶：gxf2016
c語(yǔ)言編程規(guī)范Style guidelines and programming practices for C/C++ code for Dynamic Software Solutions. Use the checklist at the end of this document prior to submitting code for peer review.
標(biāo)簽： programming guidelines Solutions for
上傳時(shí)間： 2014-07-11
上傳用戶：aeiouetla
此代碼可以實(shí)現(xiàn)以下功能 使用wordappalication 組件，代碼如下 啟動(dòng)Word時(shí)用如下代碼： begin try Wordapplication.Connect except MessageDlg(’Word may not be installed’, mtError, [mbOk], 0) Abort end Wordapplication.Visible := True WordApplication.Caption := ’Delphi automation’ end
標(biāo)簽： wordappalication 代碼
上傳時(shí)間： 2014-01-22
上傳用戶：Divine
此為編譯原理實(shí)驗(yàn)報(bào)告 學(xué)習(xí)消除文法左遞規(guī)算法，了解消除文法左遞規(guī)在語(yǔ)法分析中的作用 內(nèi)含 設(shè)計(jì)算法 目的 源碼 等等.... 算法:消除左遞歸算法為: （1）把文法G的所有非終結(jié)符按任一種順序排列成P1,P2,…Pn 按此順序執(zhí)行 （2）FOR i:=1 TO n DO BEGIN FOR j:=1 DO 把形如Pi→Pjγ的規(guī)則改寫(xiě)成 Pi→δ1γ δ2γ … δkγ。其中Pj→δ1 δ2 … δk是關(guān)于Pj的所有規(guī)則； 消除關(guān)于Pi規(guī)則的直接左遞歸性 END （3）化簡(jiǎn)由（2）所得的文法。即去除那些從開(kāi)始符號(hào)出發(fā)永遠(yuǎn)無(wú)法到達(dá)的非終結(jié)符的 產(chǎn)生規(guī)則。
標(biāo)簽： 編譯原理 實(shí)驗(yàn)報(bào)告 算法
上傳時(shí)間： 2015-03-29
上傳用戶：極客
Copyright© 2004 Sergiu Dumitriu, Marta Gî rdea, Că tă lin Hriţ cu Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License" All brand names, product names, or trademarks belong to their respective holders.
標(biāo)簽： Permission Copyright 259 Dumitriu
上傳時(shí)間： 2015-04-02
上傳用戶：jackgao
TOYFDTD1 is a stripped-down minimalist, 3D FDTD code demonstrating the basic tasks in implementing a simple 3D FDTD simulation. An idealized rectangular waveguide is modeled by treating the interior of the mesh as free space and enforcing PEC conditions on the faces of the mesh. A simplified plane wave source is inserted at one end. First released 12 April 1999. Version 1.03 released 2 December 1999.
標(biāo)簽： demonstrating stripped-down implementing minimalist
上傳時(shí)間： 2013-12-21
上傳用戶：無(wú)聊來(lái)刷下
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
