This book evolved over the past ten years from a set of lecture notes developed while teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students' background (undeveloped formal skills outside of programming), and partly to reect the maturing of the eld in GENERAL, as we have come to see it. The notes increasingly crystallized into a narrative, and we progressively structured the course to emphasize the ?story line? implicit in the progression of the material. As a result, the topics were carefully selected and clustered. No attempt was made to be encyclopedic, and this freed us to include topics traditionally de-emphasized or omitted from most Algorithms books.
標(biāo)簽： Algorithms 算法
上傳時(shí)間： 2013-11-11
上傳用戶：JamesB
西門子PLC S7-200編程軟件最新版本(2012.3) STEP7 MicroWIN_V4 SP9 完整版, 全面支持Windows7。安裝完后，打開軟件，初次為英文版，點(diǎn)擊tools（左上角自左-右第6個(gè)）然后選擇最下面的options（自上而下第15個(gè)）單擊，出現(xiàn)又一個(gè)畫面，在左邊選擇第一個(gè)選項(xiàng)GENERAL，就出現(xiàn)了語言選項(xiàng)，選擇最下面的那個(gè)（Chinese）也就是中文。然后點(diǎn)擊OK按鈕，然后一路回車下去，直到軟件關(guān)閉，再打開時(shí)就是中文的啦！
上傳時(shí)間： 2013-11-19
上傳用戶：mikesering
Altium Designer 10是由Altium公司推出的一款開發(fā)軟件，Altium Designer 10綜合了電子產(chǎn)品一體化開發(fā)所需的所有必須技術(shù)和功能。Altium Designer 在單一設(shè)計(jì)環(huán)境中集成板級(jí)和FPGA系統(tǒng)設(shè)計(jì)、基于FPGA和分立處理器的嵌入式軟件開發(fā)以及PCB版圖設(shè)計(jì)、編輯和制造。并集成了現(xiàn)代設(shè)計(jì)數(shù)據(jù)管理功能,使得Altium Designer成為電子產(chǎn)品開發(fā)的完整解決方案－一個(gè)既滿足當(dāng)前，也滿足未來開發(fā)需求的解決方案。 Altium Designer10 為您帶來了一個(gè)全新的管理元 Altium Designer release 10器件的方法。其中包括新的用途系統(tǒng)、修改管理、新的生命周期和審批制度、實(shí)時(shí)供應(yīng)鏈管理等更多的新功能! Altium Designer 10安裝流程： 安裝完后復(fù)制 AD10.Crack 文件夾下文件到安裝目錄。 1.運(yùn)行AD10KeyGen，點(diǎn)擊“打開模板”，加載license.ini，如想修改注冊(cè)名，只需修改：TransactorName=Your Name，其中Your Name用你自己的名字替換，其它參數(shù)在單機(jī)版的情況下無需修改； 2.點(diǎn)擊“生成協(xié)議”，保存生成的alf文件(文件名任意，如“jack ”)，并將其放到你的安裝目錄下； 3.將patch.exe放到你的安裝目錄下，運(yùn)行patch，對(duì)安裝目錄下的dxp.exe文件補(bǔ)丁，注意運(yùn)行破解時(shí)軟件沒有運(yùn)行； 4.啟動(dòng)DXP，運(yùn)行菜單DXP->My Account，點(diǎn)擊Add Standalone License file，加載前面生成的license（.alf）文件后即能正常使用了。 資源是.bin格式的鏡像文件，到網(wǎng)上下一個(gè)UltraISO打開后另存為iso或isz格式，用DAEMON Tools Lite虛擬光驅(qū)打開就能安裝了。(或者安裝一個(gè)快壓打開) 安裝提醒： 安裝時(shí)有兩個(gè)路徑選擇，第一個(gè)是安裝主程序的；第二個(gè)是放置設(shè)計(jì)樣例、元器件庫文件、模板文件的，共3.3GB。如果你的C盤留的不夠大，建議將3GB多的東西和主程序安裝在一塊兒。 安裝完成后界面可能是英文的，如果想調(diào)出中文界面，則可以：DXP-->Preferences-->System-->GENERAL-->Localization--選中Use localized resources，保存設(shè)置后重新啟動(dòng)程序就有中文菜單了。 Altium Designer 10破解方法： 安裝包里已經(jīng)帶有破解文件了，但沒有AD10KeyGen這個(gè)文件，所以要把注冊(cè)名改成自己的名字不方便。 1.運(yùn)行AD10KeyGen，點(diǎn)擊“打開模板”，加載license.ini，如想修改注冊(cè)名，只需修改： TransactorName=Your Name 其中Your Name用你自己的名字替換，其它參數(shù)在單機(jī)版的情況下無需修改； 2.點(diǎn)擊“生成協(xié)議”，保存生成的alf文件(文件名任意，如“jack ”)，并將其放到你的安裝目錄下； 3.將patch.exe放到你的安裝目錄下，運(yùn)行patch，對(duì)安裝目錄下的dxp.exe文件補(bǔ)丁，注意運(yùn)行破解時(shí)軟件沒有運(yùn)行； 4.啟動(dòng)DXP，運(yùn)行菜單DXP->My Account，點(diǎn)擊Add Standalone License file，加載前面生成的license（.alf）文件后即能正常使用了。 注意： 1.局域網(wǎng)內(nèi)用同一license不再提示沖突 2.僅供學(xué)習(xí)研究使用，勿用于非法用途。 相關(guān)資料：altium designer 10 破解教程
標(biāo)簽： designer altium 10 破解版
上傳時(shí)間： 2013-11-10
上傳用戶：葉立炫95
基本的編輯工具(GENERAL EDITING FACILITIES) 對(duì)象放置(Object Placement) ISIS支持多種類型的對(duì)象，每一類型對(duì)象的具體作用和功能將在下一章給出。雖然類型不同，但放置對(duì)象的基本步驟都是一樣的。 放置對(duì)象的步驟如下(To place an object:) 1.根據(jù)對(duì)象的類別在工具箱選擇相應(yīng)模式的圖標(biāo)(mode icon)。 2. Select the sub-mode icon for the specific type of object. 2、根據(jù)對(duì)象的具體類型選擇子模式圖標(biāo)(sub-mode icon)。 3、如果對(duì)象類型是元件、端點(diǎn)、管腳、圖形、符號(hào)或標(biāo)記，從選擇器里(selector)選擇你想要的對(duì)象的名字。對(duì)于元件、端點(diǎn)、管腳和符號(hào)，可能首先需要從庫中調(diào)出。 4、如果對(duì)象是有方向的，將會(huì)在預(yù)覽窗口顯示出來，你可以通過點(diǎn)擊旋轉(zhuǎn)和鏡象圖標(biāo)來調(diào)整對(duì)象的朝向。 5、最后，指向編輯窗口并點(diǎn)擊鼠標(biāo)左鍵放置對(duì)象。對(duì)于不同的對(duì)象，確切的步驟可能略有不同，但你會(huì)發(fā)現(xiàn)和其它的圖形編輯軟件是類似的，而且很直觀。 選中對(duì)象(Tagging an Object) 用鼠標(biāo)指向?qū)ο蟛Ⅻc(diǎn)擊右鍵可以選中該對(duì)象。該操作選中對(duì)象并使其高亮顯示，然后可以進(jìn)行編輯。
上傳時(shí)間： 2013-10-29
上傳用戶：avensy
Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and GENERAL recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.
標(biāo)簽： Considerations Guidelines and Design
上傳時(shí)間： 2013-11-09
上傳用戶：ls530720646
This application note provides users with a GENERAL understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
標(biāo)簽： Xilinx XAPP XSVF 503
上傳時(shí)間： 2015-01-02
上傳用戶：時(shí)代將軍
USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU GENERAL Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU GENERAL Public License for more details. ; ; You should have received a copy of the GNU GENERAL Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
上傳時(shí)間： 2013-10-29
上傳用戶：zhouchang199
LAYOUT REPORT .............. 1 目錄.................. 1 1. PCB LAYOUT 術(shù)語解釋(TERMS)......... 2 2. Test Point : ATE 測(cè)試點(diǎn)供工廠ICT 測(cè)試治具使用............ 2 3. 基準(zhǔn)點(diǎn) (光學(xué)點(diǎn)) -for SMD:........... 4 4. 標(biāo)記 (LABEL ING)......... 5 5. VIA HOLE PAD................. 5 6. PCB Layer 排列方式...... 5 7.零件佈置注意事項(xiàng) (PLACEMENT NOTES)............... 5 8. PCB LAYOUT 設(shè)計(jì)............ 6 9. Transmission Line ( 傳輸線 )..... 8 10.GENERAL Guidelines – 跨Plane.. 8 11. GENERAL Guidelines – 繞線....... 9 12. GENERAL Guidelines – Damping Resistor. 10 13. GENERAL Guidelines - RJ45 to Transformer................. 10 14. Clock Routing Guideline........... 12 15. OSC & CRYSTAL Guideline........... 12 16. CPU
上傳時(shí)間： 2013-10-29
上傳用戶：1234xhb
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while GENERAL physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of GENERAL topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
基于通用集成運(yùn)算放大器，利用MASON公式設(shè)計(jì)了一個(gè)多功能二階通用濾波器，能同時(shí)或分別實(shí)現(xiàn)低通、高通和帶通濾波，也能設(shè)計(jì)成一個(gè)正交振蕩器。電路的極點(diǎn)頻率和品質(zhì)因數(shù)能夠獨(dú)立、精確地調(diào)節(jié)。電路使用4個(gè)集成運(yùn)放、2個(gè)電容和11個(gè)電阻，所有集成運(yùn)放的反相端虛地。利用計(jì)算機(jī)仿真電路的通用濾波功能、極點(diǎn)頻率和品質(zhì)因數(shù)的獨(dú)立控制和正交正弦振蕩，從而證明該濾波器正確有效。 Abstract: A new multifunctional second-order filter based on OPs was presented by MASON formula. Functions， such as high-pass， band-pass， low-pass filtering， can be realized respectively and simultaneously， and can become a quadrature oscillator by modifying resistance ratio. Its pole angular frequency and quality factor can be tuned accurately and independently. The circuit presented contains four OPs， two capacitors， and eleven resistances， and inverting input of all OPs is virtual ground. Its GENERAL filtering， the independent control of pole frequency and quality factor and quadrature sinusoidal oscillation were simulated by computer， and the result shows that the presented circuit is valid and effective.
標(biāo)簽： MASON 多功能 二階 濾波器設(shè)計(jì)
上傳時(shí)間： 2013-10-09
上傳用戶：13788529953
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