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When a system designer specifies a nonisolated dc/dc powermodule, considering the needed input voltage range isequally as important as considering the required performanceattributes and features. Generally, nonisolated moduleshave either a narrow or a wide input voltage range. Narrowinputmodules typically have a nominal input voltage of3.3, 5, or 12 V. For systems that operate from a tightlyregulated input bus—such as those that do not use batterybackup—a narrow-input module is often adequate sincethe input remains fairly stable.Offering greater flexibility, wide-input modules operatewithin a range of 7 to 36 V, which includes the popular12- or 24-V industrial bus. This enables a single module tobe used for GENERATING multiple voltages. These modulesare ideal for industrial controls, HVAC systems, vehicles,medical instrumentation, and other applications that usea loosely regulated distribution bus. In addition, systemspowered by a rectifier/battery charger with lead-acidbattery backup almost always require wide-input modules.System designers who choose power supplies may wantto take a close look at the latest generation of wide-inputdc/dc modules.
標簽：
Wide-input
modules
offer
dc
上傳時間：
2014-12-24
上傳用戶：dragonhaixm
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The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the deviceGENERATING the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device GENERATINGthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標簽：
4channel
multiple
9544A
9544
上傳時間：
2014-12-28
上傳用戶：潛水的三貢
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The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofGENERATING interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
標簽：
Infra-red
Remote
Cont
05K
上傳時間：
2014-01-24
上傳用戶：zl5712176
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怎樣使用Nios II處理器來構建多處理器系統
Chapter 1. Creating Multiprocessor Nios II Systems
Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1
Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2
Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3
Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3
Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4
Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4
Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8
Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Software Design Considerations for Multiple Processors . . .. . . . . 1–9
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13
Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15
Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15
Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16
Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17
Getting Started with the multiprocessor_tutorial_start Design Example 1–17
Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19
Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22
Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27
GENERATING and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
標簽：
Nios
處理器
多處理器
上傳時間：
2013-11-21
上傳用戶：lo25643
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Grammatica is a C# and Java parser generator (compiler compiler). It improves upon simlar tools (like yacc and ANTLR) by creating well-commented and readable source code, by having automatic error recovery and detailed error messages, and by support for testing and debugging grammars without GENERATING source code. It supports LL(k) grammars with an unlimited number of look-ahead tokens.
標簽：
compiler
Grammatica
generator
improves
上傳時間：
2015-01-11
上傳用戶：stella2015
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The ability to create groups of reports, and grant users access to reports by group. The ability to generate reports as PDF, XLS, HTML, and CSV files. The ability to generate bar, pie and xy charts for inclusion in reports. The ability to schedule and email PDF, XLS, and CSV reports. The ability to define reusable report parameters. Available parameter types include Date, Text, and Query Parameters. The ability to create multiple DataSources for use in GENERATING reports. Support for JNDI DataSources and internal connection pooling via Commons-DBCP is included. The ability to upload and hot deploy new reports. Web based administration of users, groups, reports, parameters, and datasources. Cross platform database support via Hibernate based persistence layer. Available in a preconfigured bundle with Apache Tomcat.
標簽：
ability
reports
The
to
上傳時間：
2014-01-14
上傳用戶：franktu
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prolog 找路例子程序：
=== === === === === ===
Part 1-Adding connections
Part 2-Simple Path
example
| ?- path1(a,b,P,T).
will produce the response:
T = 15
P = [a,b] ?
Part 3 - Non-repeating path
As an example, the query:
?- path2(a,h,P,T).
will succeed and may produce the bindings:
P = [a,depot,b,d,e,f,h]
T = 155
Part 4 - GENERATING a path below a cost threshold
As an example, the query:
?- path_below_cost(a,[a,b,c,d,e,f,g,h],RS,300).
returns:
RS = [a,b,depot,c,d,e,g,f,h] ?
RS = [a,c,depot,b,d,e,g,f,h] ?
no
==================================
標簽：
Part
connections
example
prolog
上傳時間：
2015-04-24
上傳用戶：ljt101007
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亞定方程組求解：If serial correlation is found, you may have misspecified your model and
should return to your theory for a better representation of the data GENERATING
process. This possibility is quite likely and should be taken seriously.
標簽：
misspecified
correlation
serial
return
上傳時間：
2015-06-16
上傳用戶：熊少鋒
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Design Specification
Introduction
Goals and Objectives
GameForge is a graphical tool used to aid in the design and creation of video games. It attempts to bring game development down to a level that any computer savvy user can understand, without requiring masterful programming ability. A user with limited Microsoft DirectX and/or Visual C++ programming knowledge will be able to construct a basic, 2-D arcade game. GameForge limits the amount of actual code written by the user, if not eliminating it completely. It will also assist experienced programmers in GENERATING the Microsoft DirectX and Microsoft Windows9x overhead necessary for basic game construction, allowing them to concentrate on more detailed game design issues and implementation.
標簽：
Specification
Introduction
Objectives
GameForge
上傳時間：
2013-12-27
上傳用戶：wl9454
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This is a collection of m-files I created to complete a research project into the DC components of various encoding techniques. Eight of the files create random bit sequences that conform to their coding requirements. The others were files I found useful in the scope of the project and supplement the GENERATING m-files.
標簽：
collection
components
complete
research
上傳時間：
2015-12-24
上傳用戶：lnnn30
