ecos RTOS 原理介紹和應用開發The design philosophy of eCos was to augment an open-source RTOS (which meant no per-unit royalties) with source-level con?guration tools that would enable embedded developers to scale their RTOS from hundreds of bytes to hundreds of kilobytes without needing to manu- ally change a line of source code.
標簽： RTOS open-source philosophy augment
上傳時間： 2013-12-16
上傳用戶：天涯
The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
標簽： increasingly description designing languages
上傳時間： 2014-01-08
上傳用戶：小草123
This document specifies a subset of the C programming language which is intended to be suitable for embedded automotive systems up to and including safety integrity level 3 (as defined in the MISRA Guidelines). It contains a list of rules concerning the use of the C programming language together with justifications and examples.
標簽： programming specifies document language
上傳時間： 2013-12-11
上傳用戶：cursor
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary ROM 512 bytes of on-chip RAM four 8-bit bi-directional and bit-addressable I/O ports an additional 4- bit port P4 three 16-bit timer/counters a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78E58B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security
標簽： microcontroller programmable in-system W78E58B
上傳時間： 2017-04-27
上傳用戶：yiwen213
Heapsort 1.A heap is a binary tree satisfying the followingconditions: -This tree is completely balanced. -If the height of this binary tree is h, then leaves can be at level h or level h-1. -All leaves at level h are as far to the left as possible. -The data associated with all descendants of a node are smaller than the datum associated with this node. Implementation 1.using a linear array not a binary tree. -The sons of A(h) are A(2h) and A(2h+1). 2.time complexity: O(n log n)
標簽： followingconditions tree completely satisfying
上傳時間： 2017-05-25
上傳用戶：2467478207
this version is only interesting for people that want to generate their own levels (need JDK to compile new level).
標簽： interesting generate version levels
上傳時間： 2017-06-02
上傳用戶：tb_6877751
8051 assembly language source code for serial 2 chanel analog digitan converter. useful for intermediate level 8051 assembly language programmer.
標簽： for converter assembly language
上傳時間： 2017-06-10
上傳用戶：zhaoq123
實現2ASK，2FSK，2PSK，MSK，GRAY轉換自然碼
標簽： 2ASK
上傳時間： 2013-12-26
上傳用戶：h886166
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2014-01-02
上傳用戶：二驅蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2017-07-05
上傳用戶：zhoujunzhen
