眾所周知在非 Admin 用戶模式下，是不允許加載驅動執行 RING 0 代碼的。 本文提供了一種方法，通過修改系統 GDT，IDT 來添加自己的 CALLGate 和 INTGate 這樣便在系統中設置了一個后門。我們就可以利用這個后門 在任意用戶模式下執行 ring 0 代碼了。為了保證我們添加的 CALLGate 和 INT Gate 永久性。可以在第一次安裝時利用 SERVICE API 或 INF 文件設置成隨 系統啟動。不過此方法也有個缺陷，就是在第一次安裝 CALLGate 或 INTGate 時仍然需要 ADMIN 權限。下面分別給出了添加 CALLGate 與 INTGate 的具體 代碼。
上傳時間： 2016-02-14
上傳用戶：chongcongying
TFT6758液晶模塊驅動。(頭文件) 驅動芯片為HD66781 (片內224640字節GRAM,即240*(96+320)*18/8)，門驅動(Gate driver)芯片為HD66783
上傳時間： 2014-12-01
上傳用戶：1101055045
The SST89E516RDx and SST89V516RDx are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. The split-Gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST’s customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
標簽： microcontroller SST 516 RDx
上傳時間： 2014-01-08
上傳用戶：笨小孩
ili9320 datasheet. ILI9320 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel Gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit.
標簽： 9320 datasheet one-chip crystal
上傳時間： 2014-11-21
上傳用戶：jiahao131
ST7787 芯片的SPEC，比亞迪2.4inchLCM的SPEC。The ST7787 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 720 source line and 320 Gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bits/9-bits/16-bits/18-bits parallel interface. Display data can be stored in the on-chip display data RAM of 240x320x18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
上傳時間： 2016-09-22
上傳用戶：woshini123456
紅外在單片機上的應用,C語言源碼,Keil uVision3工程文件,附原理圖及說明學習文檔 紅外接收電路采用集成紅外接收器成品H1，接收器包括紅外接收管和信號處理IC，均集成在紅外接收器H1內。接收器對外只有3個引腳：Vcc、GND和一個脈沖信號輸出PO。Vcc接系統的電源正極（+5V），GND接系統的地線，脈沖信號輸出接CPU的中斷輸入引腳INT0。如果沒有紅外遙控信號到來，接收器的輸出端口PO保持高電平，當接收到紅外遙控信號時，接收器件信號轉換成脈沖序列加到CPU的中斷輸入引腳。CPU定時器T0、T1都初始化為定時器工作方式1，T0的Gate位置位，這樣T0只在INT0為高電平時計數。每次外部中斷首先停止定時，記錄T0、T1的計數值，然后將T0、T1的計數器清零，并重新啟動定時。T0的值即為高電平脈沖，T1－T0的值為低電平脈寬。 紅外發送電路是將單片機發送的信號（P2.7管腳），由一個38K的脈沖頻率進行調制，并通過一個紅外發射管發送出去。U11B和U11C及附加的電阻電容形成了一個38K脈沖發生器。
上傳時間： 2014-12-06
上傳用戶：風之驕子
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s Gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2014-01-02
上傳用戶：二驅蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s Gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2017-07-05
上傳用戶：zhoujunzhen
In this work an implementation of a geometric nonlinear controller for chaos synchronization in a Field Programmable Gate Array (FPGA) is presented. The Lorenz chaotic system is used to show the implementation of chaos synchronization via nonlinear controller implemented in a Xilinx FPGA Virtex-II 2v2000ft896-4. The main idea is to design a nonlinear geometric controller which synchronizes a slave Lorenz system to a master system and then implement them into the FPGA.
標簽： synchronization implementation controller geometric
上傳時間： 2013-12-17
上傳用戶：3到15
In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.
標簽： introduced generators implement chaotic
上傳時間： 2017-07-24
上傳用戶：qq521
