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  • Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was t

    Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was to Generate complex models with a movable camera. We wanted to be able to render complex images that consisted of hundreds to thousands of triangles. We wanted to apply interpolated shading on the objects, so that they appeared more smooth and realisitc, and to have a camera that orbitted around the object, which allowed us to look arond the object with a stationary light source. We chose to do this in hardware, because our initial implementation using running software on the NIOS II processor was too slow. Implementing parallelism in hardware is also easier to do than in software, which allows for more efficiency. We used Professor Land s floating point hardware, which allowed us to do calculations efficiency, which is essential to graphics.

    標簽: Implementation Processing Graphics rendered

    上傳時間: 2014-11-22

    上傳用戶:shawvi

  • PCI9052DemoDDK.rar

    本驅(qū)動程序?qū)τ陂_發(fā)PCI的底層協(xié)議驅(qū)動很有研究價值,能生成用戶需要的sys文件-the driver for the development of the underlying agreement PCI great research value-driven, users can Generate the necessary documents sys

    標簽: PCI DDK

    上傳時間: 2015-02-27

    上傳用戶:風之音誰懂

  • Writing Analytically ( 6th Edition )

    《分析性寫作》,介紹言簡意賅: The popular, brief rhetoric that treats writing as thinking, WRITING ANALYTICALLY, Sixth Edition, offers a series of prompts that lead you through the process of analysis and synthesis and help you to Generate original and well-developed ideas. The book's overall point is that learning to write well means learning to use writing as a way of thinking well. To that end, the strategies of this book describe thinking skills that employ writing. As you will see, this book treats writing as a tool of thought--a means of undertaking sustained acts of inquiry and reflection.

    標簽: Writing Analyticall

    上傳時間: 2015-08-22

    上傳用戶:東大寺的

  • keil單片機編寫程序

     1. 安裝Keil C51 V8.16版本,即uV3     2. 打開uVision3,點擊File---License Management...,打開License Management窗口,復制右上角的CID     3. 打開注冊機, 在CID窗口里填上剛剛復制的CID,其它設置不變     4. 點擊Generate生成許可號,復制許可號     5. 將許可號復制到License Management窗口下部的New License ID Code,點擊右側(cè)的Add LIC     6. 若上方的Product顯示的是PK51 Prof. Developers Kit即注冊成功,Support Period為有效期,一般可以到30年左右,若有效期較短,可多次生成許可號重新注冊。

    標簽: keil 單片機 注冊機

    上傳時間: 2016-02-25

    上傳用戶:woshishabi

  • RVDS2.2破解工具

    RealView Developer Suite v2.2 破解 (2009-12-11)  使用RealView Developer Suite v2.2,傳說中的RVDS 2.2,破解也有問題,經(jīng)過我琢磨。   破解步驟修改如下: 1)用Generate產(chǎn)生license file (注意自己的系統(tǒng)時間   最好是真實的當前時間,如果時間比較舊的話,產(chǎn)生的license file 將不能注冊。license file 和系統(tǒng)時間、網(wǎng)卡物理地址、硬盤的序列號有關) 2)安裝軟件 3)license Wizard     選  Install Wizard   ...   選擇license file 目錄    4)應用補丁注入工具Patch.exe給下邊列出的文件注入校驗和。文件目錄見下邊。     從這個論壇下載說明少了4個文件路徑,導致的結(jié)果就是無法啟動調(diào)試部分。   關于 no license check  out   以上作完了就加載一個*.axf文件實驗吧,看看還有沒有no license check  out  ,這時你在看軟件注冊信息 Enjoy ;-)   Install, apply our patch then Generate license file with the keygen.   -------------   the files need to be patched:      %Install Path%\IDEs\CodeWarrior\CodeWarrior\5.6.1\1592\win_32-pentium\bin\Plugins\License\oemlicense.dll   %Install Path%\IDEs\CodeWarrior\RVPlugins\1.0\86\win_32-pentium\oemlicense\oemlicense.dll   %Install Path%\RDI\armsd\1.3.1\66\win_32-pentium\armsd.exe   %Install Path%\RDI\AXD\1.3.1\98\win_32-pentium\axd.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armasm.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armcc.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armcpp.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armlink.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\fromelf.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\tcc.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\tcpp.exe   %Install Path%\RVD\Core\1.8\734\win_32-pentium\bin\tvs.exe   %Install Path%\RVD\Core\1.8\734\win_32-pentium\bin\xry100.dll

    標簽: RVDS2 破解

    上傳時間: 2017-01-18

    上傳用戶:zbxinu

  • Next Generation Mobile Broadcasting

    Mobile wireless communications are in constant evolution due to the continu- ously increasing requirements and expectations of both users and operators. Mass multimedia* services have been for a long time expected to Generate a large amount of data traffic in future wireless networks [1]. Mass multimedia services are, by definition, purposed for many people. In general, it can be distinguished between the distribution of any popular content over a wide area and the distribu- tion of location-dependent information in highly populated areas. Representative examples include the delivery of live video streaming content (like sports compe- titions, concerts, or news) and file download (multimedia clips, digital newspa- pers, or software updates).

    標簽: Broadcasting Generation Mobile Next

    上傳時間: 2020-05-31

    上傳用戶:shancjb

  • Signal Processing for Telecommunications

    This paper presents a Hidden Markov Model (HMM)-based speech enhancement method, aiming at reducing non-stationary noise from speech signals. The system is based on the assumption that the speech and the noise are additive and uncorrelated. Cepstral features are used to extract statistical information from both the speech and the noise. A-priori statistical information is collected from long training sequences into ergodic hidden Markov models. Given the ergodic models for the speech and the noise, a compensated speech-noise model is created by means of parallel model combination, using a log-normal approximation. During the compensation, the mean of every mixture in the speech and noise model is stored. The stored means are then used in the enhancement process to create the most likely speech and noise power spectral distributions using the forward algorithm combined with mixture probability. The distributions are used to Generate a Wiener filter for every observation. The paper includes a performance evaluation of the speech enhancer for stationary as well as non-stationary noise environment.

    標簽: Telecommunications Processing Signal for

    上傳時間: 2020-06-01

    上傳用戶:shancjb

  • 1 Seismic response control using electromagnetic

    This paper presents a new type of electromagnetic damper with rotating inertial mass that has been devel oped to control the vibrations of structures subjected to earthquakes. The electromagnetic inertial mass damper (EIMD) consists of a ball screw that converts axial oscillation of the rod end into rotational motion of the internal flflywheel and an electric generator that is turned by the rotation of the inner rod. The EIMD is able to Generate a large inertial force created by the rotating flflywheel and a variable damping force devel oped by the electric generator. Device performance tests of reduced-scale and full-scale EIMDs were under taken to verify the basic characteristics of the damper and the validity of the derived theoretical formulae. Shaking table tests of a three-story structure with EIMDs and earthquake response analyses of a building with EIMDs were conducted to demonstrate the seismic response control performance of the EIMD. The EIMD is able to reduce story drifts as well as accelerations and surpasses conventional types of dampers in reducing acceleration responses.

    標簽: electromagnetic response Seismic control using

    上傳時間: 2021-11-04

    上傳用戶:a1293065

  • 基于FPGA設計的字符VGA LCD顯示實驗Verilog邏輯源碼Quartus工程文件+文檔說明

    基于FPGA設計的字符VGA  LCD顯示實驗Verilog邏輯源碼Quartus工程文件+文檔說明,通過字符轉(zhuǎn)換工具將字符轉(zhuǎn)換為 8 進制 mif 文件存放到單端口的 ROM IP 核中,再從ROM 中把轉(zhuǎn)換后的數(shù)據(jù)讀取出來顯示到 VGA 上,F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。module top( input                       clk, input                       rst_n, //vga output         output                      vga_out_hs, //vga horizontal synchronization          output                      vga_out_vs, //vga vertical synchronization                   output[4:0]                 vga_out_r,  //vga red output[5:0]                 vga_out_g,  //vga green output[4:0]                 vga_out_b   //vga blue );wire                            video_clk;wire                            video_hs;wire                            video_vs;wire                            video_de;wire[7:0]                       video_r;wire[7:0]                       video_g;wire[7:0]                       video_b;wire                            osd_hs;wire                            osd_vs;wire                            osd_de;wire[7:0]                       osd_r;wire[7:0]                       osd_g;wire[7:0]                       osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r  = osd_r[7:3]; //discard low bit dataassign vga_out_g  = osd_g[7:2]; //discard low bit dataassign vga_out_b  = osd_b[7:3]; //discard low bit data//Generate video pixel clockvideo_pll video_pll_m0( .inclk0                (clk                        ), .c0                    (video_clk                  ));color_bar color_bar_m0( .clk                   (video_clk                  ), .rst                   (~rst_n                     ), .hs                    (video_hs                   ), .vs                    (video_vs                   ), .de                    (video_de                   ), .rgb_r                 (video_r                    ), .rgb_g                 (video_g                    ), .rgb_b                 (video_b                    ));osd_display  osd_display_m0( .rst_n                 (rst_n                      ), .pclk                  (video_clk                  ), .i_hs                  (video_hs                   ), .i_vs                  (video_vs                   ), .i_de                  (video_de                   ), .i_data                ({video_r,video_g,video_b}  ), .o_hs                  (osd_hs                     ), .o_vs                  (osd_vs                     ), .o_de                  (osd_de                     ), .o_data                ({osd_r,osd_g,osd_b}        ));endmodule

    標簽: fpga vga lcd

    上傳時間: 2021-12-18

    上傳用戶:

  • 基于FPGA設計的vga顯示測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明 FPGA

    基于FPGA設計的vga顯示測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明,F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。module top( input                       clk, input                       rst_n, //vga output         output                      vga_out_hs, //vga horizontal synchronization          output                      vga_out_vs, //vga vertical synchronization                   output[4:0]                 vga_out_r,  //vga red output[5:0]                 vga_out_g,  //vga green output[4:0]                 vga_out_b   //vga blue );wire                            video_clk;wire                            video_hs;wire                            video_vs;wire                            video_de;wire[7:0]                       video_r;wire[7:0]                       video_g;wire[7:0]                       video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r  = video_r[7:3]; //discard low bit dataassign vga_out_g  = video_g[7:2]; //discard low bit dataassign vga_out_b  = video_b[7:3]; //discard low bit data//Generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule

    標簽: fpga vga顯示 verilog quartus

    上傳時間: 2021-12-19

    上傳用戶:kingwide

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